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21

HMC987LP5E

v01.0512

LOW NOISE 1:9 FANOUT BUFFER

DC - 8 GHz

the Master (host), on the first 9 falling edges of sClk places 9 bit data, d8:d0, Msb first, on sDi as shown in

Figure 39. d8:d0 should be set to zero. d3:d0 = address of the register to be rEAD on the next cycle.

a. the slave () shifts in data on sDi on the first 9 rising edges of sClk

b. Master places 4 bit register address , r3:r0, ( the address the WritE ADDrEss register), Msb first, on the

next 4 falling edges of sClk (10-13). r3:r0=0000.

c. slave shifts the register bits on the next 4 rising edges of sClk (10-13).

d. Master places 3 bit chip address, a2:a0, Msb first, on the next 3 falling edges of sClk (14-16).

e. slave shifts the chip address bits on the next 3 rising edges of sClk (14-16).

f.

Master asserts sEn after the 16th rising edge of sClk.

g. slave registers the sDi data on the rising edge of sEn.

h. Master clears sEn to complete the address transfer of the two part rEAD cycle.

i.

if we do not wish to write data to the chip at the same time as we do the second cycle , then it is

recommended to simply rewrite the same contents on sDi to register zero on the rEAD back part of the

cycle.

j.

Master places the same sDi data as the previous cycle on the next 16 falling edges of sClk.

k. slave () shifts the sDi data on the next 16 rising edges of sClk.

l.

slave places the desired data (i.e. data from address in reg00h[3:0]) on sDo on the next 16 rising edges of

sClk.

m. Master asserts sEn after the 16th rising edge of sClk to complete the cycle.

note that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the sDo output to prevent a possible

bus contention issue.

Table 8. SPI Open Mode - Read Timing Characteristics

Parameter

Conditions

Min.

typ.

Max.

units

t1

t2

t3

t4

t5

t6

t7

sDi setup time

sDi hold time

sEn low duration

sEn high duration

sClk rising Edge to sDo time

sEn to sClk recovery time

sClk 16 rising Edge to sEn rising Edge

3

3

10

10

10

10

8.2+0.2ns/pF

ns

ns

ns

ns

ns

ns

ns