DM9016 datasheet(30/85 Pages) DAVICOM

30 / 85 page

DM9016

3-port switch with Processor Interface

Preliminary datasheet

DM9016-13-DS-P01

March 26, 2009

6.38 Switch Control Register (52H)

Bit

Name

Default

Description

MEM_BIST

PH0,RO

Address Memory Test BIST Status

0: OK

1: Fail

RST_SW

P0,RW

Reset Switch Core

Write 1 to launch and clear automatically after 10us.

RST_ANLG

P0,RW

Reset Analog PHY Core

Write 1 to launch and clear automatically after 10us.

4:3

SNF_PORT

PHE00,RW Sniffer Port Number

CRC_DIS

PHE0,RW

Switch CRC Checking Disable

1:0

RESERVED

0,RO

Reserved

6.39 VLAN Control Register (53H)

Bit

Name

Default

Description

TOS6

PHE0,RW Full ToS Using Enable

0: check most significant 3-bit only of TOS

1: check most significant 6-bit of TOS

RESERVED

0,RO

Reserved

UNICAST

PHE0,RW Unicast Packet Can Across VLAN Boundary

VIDFFF

PHE0,RW Replace VID FFF

VID1

PHE0,RW Replace VID 001

VID0

PHE0,RW Replace VID 000

PRI

PHE0,RW Replace Priority Field in The Tag

VLAN

PHE0,RW VLAN Mode Enable

0: port-base VLAN

1: 802.1Q base VLAN mode enable

6.41 Bandwidth LED Control Register (55H)

Bit

Name

Default

Description

7,6

RESERVED

PH0,RW

Reserved

P2_TX

PH1,RW

Port 2 transmit as event of bandwidth LED source

P2_RX

PH0,RW

Port 2 receive as event of bandwidth LED source

P1_TX

PH1,RW

Port 1 transmit as event of bandwidth LED source

P1_RX

PH0,RW

Port 1 receive as event of bandwidth LED source

P0_TX

PH1,RW

Port 0 transmit as event of bandwidth LED source

P0_RX

PH0,RW

Port 0 receive as event of bandwidth LED source

6.42 STP Control Register (56H)

Bit

Name

Default

Description

7:1

RESERVED

0,RO

Reserved

STPEN

PS0,RW

Spanning Tree Protocol Enabled

6.43 DSP PHY Control Register (58H~59H)

58H:

Bit

Name

Default

Description

7:0

DSP_CTL1

PH0,RW

DSP Control Register 1 for testing only (register 58H)

DM9016 Datasheet(PDF) 30 Page - Davicom Semiconductor, Inc.

DM9016 Datasheet(HTML) 30 Page - Davicom Semiconductor, Inc.

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