DM9161CIEP datasheet(32/47 Pages) DAVICOM

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DM9161CI

10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver

Final

Version: DM9161CI-DS-F01

February 22, 2012

8.10 10BASE-T Configuration/Status (10BTCSR) - 18

Bit

Bit Name

Default

Description

18.15

Reserved

0, RO

Reserved

Read as 0, ignore on write

18.14

LP_EN

1, RW

Link Pulse Enable

1 = Transmission of link pulses enabled

0 = Link pulses disabled, good link condition forced

This bit is valid only in 10Mbps operation

18.13

HBE

1,RW

Heartbeat Enable

1 = Heartbeat function enabled

0 = Heartbeat function disabled

When the DM9161CI is configured for full duplex operation, this bit will

be ignored (the collision/heartbeat function is invalid in full duplex

mode)

18.12

SQUELCH

1, RW

Squelch Enable

1 = Normal squelch

0 = Low squelch

18.11

JABEN

1, RW

Jabber Enable

Enables or disables the Jabber function when the DM9161CI is in

10BASE-T full duplex or 10BASE-T transceiver Loopback mode

1 = Jabber function enabled

0 = Jabber function disabled

18.10

10BT_SER

(#PIN

34),RW

10BASE-T GPSI Mode ( Default value depend on #pin34 strap

condition)

1 = 10BASE-T GPSI mode selected (#pin34 pull down)

0 = 10BASE-T MII mode selected (#pin34 pull up, default)

GPSI mode is not supported for 100Mbps operation

18.9-18.1

Reserved

0, RO

Reserved

Read as 0, ignore on write

18.0

POLR

0, RO

Polarity Reversed

When this bit is set to 1, it indicates that the 10Mbps cable polarity is

reversed. This bit is automatically set and cleared by 10BASE-T

module

8.11 Power

down Control Register (PWDOR) - 19

Bit

Bit Name

Default

Description

19.15-19.9

Reserved

0, RO

Reserved

Read as 0, ignore on write

19.8

PD10DRV

0, RW