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TLC5948APWPR Datasheet(PDF) 13 Page - Texas Instruments |
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TLC5948APWPR Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 50 page  TLC5948A www.ti.com SBVS192 – MARCH 2012 PIN DESCRIPTIONS PIN NAME NO. I/O DESCRIPTION GND 1 — Power ground Grayscale (GS) pulse width modulation (PWM) reference clock control for OUTn. When BLANK = 0, each GSCLK rising edge increments the GS counter for PWM control. GSCLK 21 I When BLANK = 0, all constant-current outputs (OUT0 to OUT15) are forced off, the GS counter is reset to '0', and the GS PWM timing controller is initialized. Reference current terminal. A resistor connected between IREF to GND sets the maximum current for all constant-current outputs. IREF 23 I/O When IREF is shorted to GND with low resistance, all constant-current outputs are forced off and the IREF short flag (ISF) bit in the status information data (SID) is set to '1'. The LAT rising edge either latches the data from the 257-bit common shift register into the first GS data latch when the common shift register MSB is '0' or it latches the data into the first control data latch when the common shift register MSB is '1'. LAT 4 I When the display timing reset bit (TMGRST) in the first control data latch is '1', the GS counter is initialized at the LAT signal for GS data writes. At the same time, the data in the 257-bit common shift register are copied to the first and second GS data latches simultaneously and the DC and BC data in the first control data latch are copied to the second data latch. OUT0 5 O OUT1 6 O OUT2 7 O OUT3 8 O OUT4 9 O OUT5 10 O OUT6 11 O Constant-current outputs. OUT7 12 O Multiple outputs can be configured in parallel to increase the constant-current capability. OUT8 13 O Different voltages can be applied to each output. OUT9 14 O OUT10 15 O OUT11 16 O OUT12 17 O OUT13 18 O OUT14 19 O OUT15 20 O Serial data shift clock. Data present on SIN are shifted to the 257-bit common shift register LSB with the SCLK rising edge. SCLK 3 I Data in the shift register are shifted towards the MSB at each SCLK rising edge. The common shift register MSB appears on SOUT. SIN 2 I 257-bit common shift register serial data input. 257-bit common shift register serial data output. LED open detection (LOD), LED short detection (LSD), output leak detection (OLD), thermal error flag (TEF), and the IREF pin short flag (ISF) bit can be read out with SOUT as SID after the LAT rising SOUT 22 O edge. SOUT is connected to the 257-bit common shift register MSB. Data are clocked out at the SCLK rising edge. VCC 24 — Power-supply voltage Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): TLC5948A |
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