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LT3510

3510fe

the output capacitor integrates this current, and that the

capacitor on the VC pin (CC) integrates the error ampli-

ﬁer output current, resulting in two poles in the loop. In

most cases a zero is required and comes from either the

output capacitor ESR or from a resistor in series with CC.

This simple model works well as long as the value of the

inductor is not too high and the loop crossover frequency

is much lower than the switching frequency. A phase lead

capacitor (CPL) across the feedback divider may improve

the transient response.

Synchronization

The RT/SYNC pin can be used to synchronize the regulators

to an external clock source. Driving the RT/SYNC resistor

with a clock source triggers the synchronization detection

circuitry. Once synchronization is detected, the rising edge

of SW1 will be synchronized to the rising edge of the

RT/SYNC pin signal. An AGC loop will adjust the internal

oscillators to maintain a 180 degree phase between SW1

and SW2, and also adjust slope compensation to avoid

subharmonic oscillation.

The synchronizing clock signal input to the LT3510 must

have a frequency between 250kHz and 1.5MHz, a duty

cycle between 20% and 80%, a low state below 0.5V and

a high state above 1.6V. Synchronization signals outside

of these parameters will cause erratic switching behavior.

The RT/SYNC resistor should be set such that the free

running frequency ((VRT/SYNC – VSYNCLO)/RRT/SYNC) is

approximately equal to the synchronization frequency. If

the synchronization signal is halted, the synchronization

detection circuitry will timeout in typically 10μs at which

time the LT3510 reverts to the free-running frequency

based on the current through RT/SYNC. If the RT/SYNC

resistor is held above 2V at any time, switching will be

disabled.

If the synchronization signal is not present during regula-

tor start-up (for example, the synchronization circuitry is

powered from the regulator output) the RT/SYNC pin must

see an equivalent resistance to ground between 15.4k and

133k until the synchronization circuitry is active for proper

start-up operation.

If the synchronization signal powers up in an undetermined

state (VOL, VOH, Hi-Z), connect the synchronization clock

to the LT3510 as shown in Figure 7. The circuit as shown

will isolate the synchronization signal when the output

voltage is below 90% of the regulated output. The LT3510

will start-up with a switching frequency determined by the

resistor from the RT/SYNC pin to ground.

If the synchronization signal powers up in a low impedance

state (VOL), connect a resistor between the RT/SYNC pin

and the synchronizing clock. The equivalent resistance

seen from the RT/SYNC pin to ground will set the start-up

frequency.

Figure 6. Model for Loop Response

Figure 7. Synchronous Signal Powered from Regulator’s Output

0.8V

LT3510

CPL

OUTPUT

3510 F06

ESR

TANTALUM

POLYMER

CERAMIC

ERROR

AMP

gm = 275μmho

CURRENT MODE

POWER STAGE

gm = 2.2mho

3.6M

LT3510

SYNCHRONIZATION

CIRCUITRY

VOUT1

RT/SYNC

3510 F07

VCC

CLK

PG1

APPLICATIONS INFORMATION

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