LTC1865 datasheet(9/18 Pages) LINER

9 / 18 page

LTC2356-12/LTC2356-14

2356fb

2356 BD

–

S & H

GND

EXPOSED PAD

LTC2356-14

VREF

10µF

AIN–

AIN+

14-BIT ADC

3.3V

10µF

THREE-

STATE

SERIAL

OUTPUT

PORT

2.5V

REFERENCE

TIMING

LOGIC

VDD

SDO

CONV

SCK

PIN FUNCTIONS

AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates

fully differentially with respect to AIN– with a –1.25V to

1.25V differential swing with respect to AIN– and a 0V to

VDD common mode swing.

AIN– (Pin 2): Inverting Analog Input. AIN– operates fully

differentially with respect to AIN+ with a 1.25V to –1.25V

differential swing with respect to AIN+ and a 0V to VDD

common mode swing.

VREF (Pin 3): 2.5V Internal Reference. Bypass to GND

and to a solid analog ground plane with a 10µF ceramic

capacitor(or10µFtantaluminparallelwith0.1µFceramic).

Can be overdriven by an external reference between 2.55V

and VDD.

GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These

ground pins and the exposed pad must be tied directly to

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

flow through these pins.

VDD (Pin 7): 3.3V Positive Supply. This single power pin

supplies 3.3V to the entire device. Bypass to GND and to

a solid analog ground plane with a 10µF ceramic capacitor

(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in

mind that internal analog currents and digital output signal

currents flow through this pin. Care should be taken to

place the 0.1µF bypass capacitor as close to Pins 6 and

7 as possible.

SDO (Pin 8): Three-State Serial Data Output. Each set

of output data words represents the difference between

AIN+ and AIN– analog inputs at the start of the previous

conversion. The output format is 2’s complement.

SCK (Pin 9): External Clock Input. Advances the conver-

sion process and sequences the output data on the rising

edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels.

One or more pulses wake from sleep.

CONV(Pin10):ConvertStart.Holdstheanaloginputsignal

and starts the conversion on the rising edge. Responds

to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses

with SCK in fixed high or fixed low state start Nap mode.

Four or more CONV pulses with SCK in fixed high or fixed

low state start Sleep mode.

BLOCK DIAGRAM

LTC1865 Datasheet(PDF) 9 Page - Linear Technology

LTC1865 Datasheet(HTML) 9 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL