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LTC3833 Datasheet(PDF) 3 Page - Linear Technology |
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LTC3833 Datasheet(HTML) 3 Page - Linear Technology |
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3 / 50 page  LTC3839 3 3839fa SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IVOUTSENSE+ VOUTSENSE+ Input Bias Current VOUTSENSE+ – VOUTSENSE– = 0.6V ±5 ±25 nA IVOUTSENSE– VOUTSENSE– Input Bias Current VOUTSENSE+ – VOUTSENSE– = 0.6V –25 –50 μA gm(EA) Error Amplifier Transconductance ITH = 1.2V (Note 5) 1.7 mS tON(MIN)1,2 Minimum Top Gate On-Time VIN = 38V, VOUT = 0.6V, RT = 20k (Note 6) 30 ns tOFF(MIN)1,2 Minimum Top Gate Off-Time (Note 6) 90 ns Current Sensing VSENSE(MAX)1,2 Maximum Valley Current Sense Threshold (VSENSE1,2+ – VSENSE1,2–) VRNG = 2V, VFB = 0.57V, VSENSE– = 2.5V VRNG = 0V, VFB = 0.57V, VSENSE– = 2.5V VRNG = INTVCC, VFB = 0.57V, VSENSE– = 2.5V l l l 80 21 39 100 30 50 120 40 61 mV mV mV VSENSE(MIN)1,2 Minimum Valley Current Sense Threshold (VSENSE1,2+ – VSENSE1,2–) (Forced Continuous Mode) VRNG = 2V, VFB = 0.63V, VSENSE– = 2.5V VRNG = 0V, VFB = 0.63V, VSENSE– = 2.5V VRNG = INTVCC, VFB = 0.63V, VSENSE– = 2.5V –50 –15 –25 mV mV mV ISENSE1,2+ SENSE1,2+ Pins Input Bias Current VSENSE+ = 0.6V VSENSE+ = 5V ±5 1 ±50 ±2 nA μA ISENSE1,2– SENSE1,2– Pins Input Bias Current (Internal 500k Resistor to SGND) VSENSE– = 0.6V VSENSE– = 5V 1.2 10 μA μA Start-Up and Shutdown VRUN RUN Pin On Threshold VRUN Rising l 1.1 1.2 1.3 V RUN Pin On Hysteresis VRUN Falling from On Threshold 100 mV IRUN RUN Pin Pull-Up Current when Off RUN = SGND 2.5 μA RUN Pin Pull-Up Current Hysteresis (IRUN(ON) – IRUN(OFF))10 μA UVLO INTVCC Undervoltage Lockout INTVCC Falling INTVCC Rising l l 3.3 3.7 4.2 4.5 V V ITRACK/SS Soft-Start Pull-Up Current 0V < TRACK/SS < 0.6V 1 μA Frequency and Clock Synchronization f Clock Output Frequency (Steady-State Switching Frequency) RT = 205k RT = 80.6k RT = 18.2k 450 200 500 2000 550 kHz kHz kHz Channel 2 Phase (Relative to Channel 1) PHASMD = SGND PHASMD = Floating PHASMD = INTVCC 180 180 240 Deg Deg Deg CLKOUT Phase (Relative to Channel 1) PHASMD = SGND PHASMD = Floating PHASMD = INTVCC 60 90 120 Deg Deg Deg VPLLIN(H) Clock Input High Level Into MODE/PLLIN 2 V VPLLIN(L) Clock Input Low Level Into MODE/PLLIN 0.5 V RMODE/PLLIN MODE/PLLIN Input Resistance With Respect to SGND 600 kΩ Gate Drivers RTG(UP)1,2 TG Driver Pull-Up On Resistance TG High 2.5 Ω RTG(DOWN)1,2 TG Driver Pull-Down On Resistance TG Low 1.2 Ω RBG(UP)1,2 BG Driver Pull-Up On Resistance BG High 2.5 Ω RBG(DOWN)1,2 BG Driver Pull-Down On Resistance BG Low 0.8 Ω tD(TG/BG)1,2 Top Gate Off to Bottom Gate On Delay Time (Note 6) 20 ns tD(BG/TG)1,2 Bottom Gate Off to Top Gate On Delay Time (Note 6) 15 ns ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted (Note 3). |
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