LTM2881 datasheet(13/24 Pages) LINER

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LTM2881

2881fe

reduce EMI emissions from equipment and data cables.

The reduced slew rate mode is entered by taking the SLO

pin low to GND2, where the data rate is limited to about

250kbps. Slew limiting also mitigates the adverse effects

of imperfect transmission line termination caused by stubs

or mismatched cables.

Figures 9a and 9b show the frequency spectrums of the

LTM2881 driver outputs in normal and SLO mode operat-

ing at 250kbps. SLO mode significantly reduces the high

frequency harmonics.

Receiver and Failsafe

With the receiver enabled, when the absolute value of the

differential voltage between the A and B pins is greater than

200mV, the state of RO will reflect the polarity of (A-B).

During data communication the receiver detects the state

of the input with symmetric thresholds around 0V. The

symmetric thresholds preserve duty cycle for attenu-

ated signals with slow transition rates on high capacitive

busses, or long cable lengths. The receiver incorporates

a failsafe feature that guarantees the receiver output to

be a logic-high during an idle bus, when the inputs are

shorted, left open or terminated, but not driven. The failsafe

feature eliminates the need for system level integration of

network pre-biasing by guaranteeing a logic-high on RO

under the conditions of an idle bus. Further network bias-

ing constructed to condition transient noise during an idle

state is unnecessary due to the common mode transient

rejection of the LTM2881. The failsafe detector monitors

A and B in parallel with the receiver and detects the state

APPLICATIONS INFORMATION

Figure 9a. Frequency Spectrum SLO Mode 125kHz Input

Figure 9b. Normal Mode Frequency Spectrum 125kHz Input

FREQUENCY (MHz)

2881 F09a

12.5

6.25

FREQUENCY (MHz)

2881 F09b

12.5

6.25

of the bus when A-B is above the input failsafe threshold

for longer than about 3μs with a hysteresis of 25mV. This

failsafe feature is guaranteed to work for inputs spanning

the entire common mode range of –7V to 12V.

The receiver output is internally driven high (to VL) or

low (to GND) with no external pull-up needed. When the

receiver is disabled the RO pin becomes Hi-Z with leakage

of less than ±1μA for voltages within the supply range.

Receiver Input Resistance

The receiver input resistance from A or B to GND2 is

greater than 96k permitting up to a total of 256 receivers

per system without exceeding the RS485 receiver loading

specification. High temperature H-/MP-Grade operation

reduces the input resistance to 48k permitting 128 re-

ceivers on the bus. The input resistance of the receiver is

unaffected by enabling/disabling the receiver or by power-

ing/unpowering the part. The equivalent input resistance

looking into A and B is shown in Figure 10.

Figure 10. Equivalent Input Resistance into A and B

60Ω

2881 F10

>96k

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