SPEC NO. 05-08-5223 REV. B

RH1573K LOW DROPOUT PNP REGULATOR DRIVER DICE

LINEAR TECHNOLOGY CORPORATION

5.1

100 Percent Visual Inspection: All dice supplied to this specification shall be inspected in accordance

with MIL-STD-883, Method 2010, Condition A. All reject dice shall be removed from the lot.

5.2

Electrical Performance Characteristics for Element Evaluation: The electrical performance

characteristics shall be as specified in Table I, Table II and Table III herein.

5.3

Sample Testing: Each wafer supplying dice for delivery to this specification shall be subjected to

element evaluation sample testing. No dice shall be delivered until all the lot sample testing has been

performed and the results found to be acceptable unless the customer supplies a written approval for

shipment prior to completion of wafer qualification as specified in this specification.

5.4

Part Marking of Element Evaluation Sample Includes:

5.4.1

LTC Logo

5.4.2

LTC Part Number

5.4.3

Date Code

5.4.4

Serial Number

5.4.5

ESD Identifier per MIL-PRF-38535, Appendix A

5.4.6

Diffusion Lot Number

5.4.7

Wafer Number

5.5

Burn-In Requirement: Burn-In circuit for CERDIP / 8 lead package is specified in Figure 3.

5.6

Mechanical/Packaging Requirements: Case Outline and Dimensions are in accordance with

Figure 4.

5.7

Terminal Connections: The terminal connections shall be as specified in Figure 5.

5.8

Lead Material and Finish: The lead material and finish shall be alloy 42 with hot solder dip (Finish

letter A) in accordance with MIL-PRF-38535.

6.0

VERIFICATION (QUALITY ASSURANCE PROVISIONS)

6.1

Quality Assurance Provisions: Quality Assurance provisions shall be in accordance with MIL-PRF-

38535. Linear Technology is a QML certified company and all Rad Hard candidates are assembled on

qualified Class S manufacturing lines.

6.2

Sampling and Inspection: Sampling and Inspection shall be in accordance with Table III herein.

6.3

Screening: Screening requirements shall be in accordance with Table III herein.

6.4

Source Inspection:

6.4.1

The manufacturer will coordinate Source Inspection at wafer lot acceptance and pre-seal

internal visual.