MKG-16487 Ver. 5.0

10

Qualcomm Atheros, Inc.

MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION

3

WiFi Functional Description

3.1 Overview

The AR4100 is a single chip 802.11 b/g/n device optimized for low power embedded applications.

The data path consists of the host interface, mailbox DMA, AHB, memory controller, MAC, BB,

and radio. The CPU drives the control path via register and memory accesses.

3.2 XTENSA CPU

At the heart of the chip is the XTENSA CPU. The CPU has these interfaces:



Code RAM/ROM interface (iBus), going to the virtual memory controller (VMC)



Data RAM interface (dBus), going to the VMC

3.3 Reset Control

The AR4100 CHIP_PWD_L pin can be used to completely reset the entire chip. After this signal

has been de-asserted, the AR4100 waits for host communication. Until then, the MAC, BB, and

SOC blocks are powered off and all modules except the host interface are held in reset.

Once the host has initiated communication, the AR4100 turns on its crystal and later on its PLL.

After all clocks are stable and running, the resets to all blocks are automatically de-asserted. The

only resets that stay asserted are:



Warm and cold resets to the MAC



Warm reset to the radio (The cold reset gets automatically de-asserted)

The above resets are deasserted by software. All AR4100 reset control logic resides in the RTC

block to ensure stable reset generation.

3.3.1

CPU Reset

CPU reset is different from the other resets mentioned above. There four scenarios are where the

CPU reset can be asserted:

1. The CHIP_PWD_L pin is asserted or the host has not initiated communication.

2. The polarity of certain package pins are set to enable JTAG debugging via an In-Circuit

Emulator (ICE). In this case, the external ICE can assert CPU reset through a package pin.

3. The polarity of a package pin is set to hold the CPU in reset until the host clears an internal

AR4100 register.

4. An internal AR4100 register is set by the host to force the CPU out of an unknown state.