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MK50DX256CLL10 Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc |
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MK50DX256CLL10 Datasheet(HTML) 73 Page - Freescale Semiconductor, Inc |
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73 / 79 page ![]() 8.1 K50 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 100 LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 1 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA RTC_CLKOUT 2 PTE1/ LLWU_P0 ADC1_SE5a ADC1_SE5a PTE1/ LLWU_P0 SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL SPI1_SIN 3 PTE2/ LLWU_P1 ADC1_SE6a ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_CTS_b SDHC0_DCLK 4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_b SDHC0_CMD SPI1_SOUT 5 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3 6 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 7 VDD VDD VDD 8 VSS VSS VSS 9 USB0_DP USB0_DP USB0_DP 10 USB0_DM USB0_DM USB0_DM 11 VOUT33 VOUT33 VOUT33 12 VREGIN VREGIN VREGIN 13 ADC0_DP1/ OP0_DP0 ADC0_DP1/ OP0_DP0 ADC0_DP1/ OP0_DP0 14 ADC0_DM1/ OP0_DM0 ADC0_DM1/ OP0_DM0 ADC0_DM1/ OP0_DM0 15 ADC1_DP1/ OP1_DP0/ OP1_DM1 ADC1_DP1/ OP1_DP0/ OP1_DM1 ADC1_DP1/ OP1_DP0/ OP1_DM1 16 ADC1_DM1/ OP1_DM0 ADC1_DM1/ OP1_DM0 ADC1_DM1/ OP1_DM0 17 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 18 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 19 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 20 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 21 VDDA VDDA VDDA 22 VREFH VREFH VREFH 23 VREFL VREFL VREFL 24 VSSA VSSA VSSA Pinout K50 Sub-Family Data Sheet, Rev. 1, 6/2012. Freescale Semiconductor, Inc. Preliminary 73 General Business Information |
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