MK50DX256CMB7 datasheet(63/78 Pages) FREESCALE

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DS3

DS4

DS1

DS2

DS7

DS8

First data

Last data

DS5

First data

Data

Last data

DS6

Data

DSPI_PCSn

DSPI_SCK

(CPOL=0)

DSPI_SIN

DSPI_SOUT

Figure 23. DSPI classic SPI timing — master mode

Table 47. Slave mode DSPI timing (full voltage range)

Num

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

Frequency of operation

—

6.25

MHz

DS9

DSPI_SCK input cycle time

8 x tBUS

—

DS10

DSPI_SCK input high/low time

(tSCK/2) - 4

(tSCK/2) + 4

DS11

DSPI_SCK to DSPI_SOUT valid

—

DS12

DSPI_SCK to DSPI_SOUT invalid

—

DS13

DSPI_SIN to DSPI_SCK input setup

—

DS14

DSPI_SCK to DSPI_SIN input hold

—

DS15

DSPI_SS active to DSPI_SOUT driven

—

DS16

DSPI_SS inactive to DSPI_SOUT not driven

—

First data

Last data

First data

Data

Last data

Data

DS15

DS10

DS9

DS16

DS11

DS12

DS14

DS13

DSPI_SS

DSPI_SCK

(CPOL=0)

DSPI_SOUT

DSPI_SIN

Figure 24. DSPI classic SPI timing — slave mode

Peripheral operating requirements and behaviors

K50 Sub-Family Data Sheet, Rev. 2, 4/2012.

Freescale Semiconductor, Inc.

MK50DX256CMB7 Datasheet(PDF) 63 Page - Freescale Semiconductor, Inc

MK50DX256CMB7 Datasheet(HTML) 63 Page - Freescale Semiconductor, Inc

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