EUP3427

DS3427

Ver1.0

Jul. 2011

2

Typical Application Circuit (continued)

Figure2. TDFN-10 Typical Application Circuit

Pin Configurations

Package

Type

Pin Configurations

Package

Type

Pin Configurations

SOP-8 (EP)

TDFN-10

Pin Description

PIN

SOP-8 (EP) TDFN-10

DESCRIPTION

LX

1

2,3

Switch node connected to inductor. This pin is connected to the drains of the

internal main and synchronous power MOSFET switches.

SKIP

2

7

Operation Mode Select Input. Logic high selects pulse skipping mode, and

logic low or floating chooses forced PWM mode. An internal 5µA current pull

it down to ground.

EN

3

5

Chip enable pin. Forcing this pin above 1.5V enables the part. Forcing this pin

below 0.3V or floating it shuts down the device.An internal 600k

Resistor

pulls it down to ground.

PG

4

4

Power good output signal. Logic high when regulator output is within ±10%

of target output voltage. A pull-up resistor of 10k

to 100k

is recommended

for most applications.

AGND

5

-

Analog ground.

FB

6

6

Feedback pin. Connect it to an external resistor divider to set output voltage.

PVIN

7

9,10

Power supply input.

PGND

8

-

Power ground.

SVIN

-

8

Analog input supply which is connected to PVIN through a low pass RC filter.

NC

-

1

No connect.

Thermal

Pad

-

-

Ground.( Thermal pad must be connected to the ground of PCB.)