MMA6525KW datasheet(34/56 Pages) FREESCALE

34 / 56 page

Sensor

Freescale Semiconductor, Inc.

MMA65xx

3.8.4

Offset Cancellation

The device provides the option to read offset cancelled acceleration data via the SPI by clearing the OC bit in the DEVCFG

register (reference Section 3.1.6.1) and in the SPI command (reference Section 4.1). A block diagram of the offset cancellation

is shown in Figure 21, and response parameters are specified in Section 2.4 and in Table 28.

Figure 21. Offset Cancellation Block Diagram

In normal operation, the offset cancellation circuit computes a 24,576 sample running average of the acceleration data down-

sampled to 256

μs. The running average is compared against positive and negative thresholds to determine the offset correction

value that will be applied to the acceleration data.

During start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals. Ref-

erence Table 28 for offset cancellation timing information during startup and normal operation. The offset cancellation startup

phase can also be directly controlled during initialization (ENDINIT = ‘0’) using the OCPHASE[1:0] bits and the OFFCFG_EN bit

in the DEVCTL register, as described in Section 3.1.5.2 and Section 3.1.5.3.

When the self test circuitry is active, the offset cancellation block and the offset monitor block are suspended, and the offset

correction value is constant. Once the self test circuitry is disabled, the offset cancellation block remains suspended for the time

tST_OMB to allow the acceleration output to return to it’s nominal offset.

3.8.5

Offset Monitor

The device provides the option for an offset monitor circuit. The offset monitor circuit is enabled when the OFMON bit in the

DEVCFG register is programmed to a logic ‘1’. The output of the offset cancellation circuit is compared against a high and low

threshold. If the offset correction value exceeds either the OFFTHRPOS, or OFFTHRNEG threshold, an Offset Over Range Error

condition is indicated.

The offset correction value update rate is listed in Table 28: “Maximum Slew Rate”. Because the offset monitor uses this value,

the offset monitor will also update at this rate. The time to indicate an Offset Over Range Error is dependent upon the input signal.

The offset monitor status remains suspended during self test, because the offset monitor is based on the offset cancellation

circuit, which is also suspended during self test. The offset monitor is disabled for 2.1 seconds following reset regardless of the

state of the OFMON bit.

Table 28. Offset Cancellation Timing Specifications

Phase

Start Time of

Phase

(from POR)

Typical

Time in

Phase (ms)

# of Samples in

Phase

Samples

Averaged

OFF_CORR_VALUE

Update Rate

(ms)

Averaging

Period

(ms)

Maximum

Slew Rate

(LSB/s)

Averaging Filter

-3dB Frequency

(Hz)

Start 1

tOP

524.288

2048

2.048

12.288

122.1

36.05

Start 2

tOP + 524.288

524.288

2048

384

16.38

98.304

15.26

4.506

Start 3

tOP + 1048.576

524.288

2048

3072

131.1

786.432

1.907

0.5632

Normal

tOP + 1572.864

—

24576

1049

6291.456

0.2384

0.07040

Accumulator

4096 samples

Shift

LPFOUT

Offset Inc/Dec

OFFCORRP

OFFCORRN

1/8 LSB

Increment 1/4 LSB

Downsampled to 256

μs

OFF_CORR_VALUE

OFFTHRNEG

OFFTHRPOS

OFF_ERR

Alignment

Correction

1.049s

T Registers updated every 1.049s

Decrement 1/4 LSB

6.291s Average

Updated every 1.049s

OCOUT

MMA6525KW Datasheet(PDF) 34 Page - Freescale Semiconductor, Inc

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