TLE4271G datasheet(3/20 Pages) SIEMENS

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TLE 4271

Semiconductor Group

1998-11-01

Application Description

The IC regulates an input voltage in the range of 5.5 V <

I < 36 V to VQnom = 5.0 V. Up

to 26 V it produces a regulated output current of more than 550 mA. Above 26 V the

save-operating-area protection allows operation up to 36 V with a regulated output

current of more than 300 mA. Overvoltage protection limits operation at 42 V. The

overvoltage protection hysteresis restores operation if the input voltage has dropped

below 36 V. The IC can be switched off via the inhibit input, which causes the quiescent

current to drop below 50

µA. A reset signal is generated for an output voltage of

Q < 4.5 V. The watchdog circuit monitors a connected controller. If there is no positive-

going edge at the watchdog input within a fixed time, the reset output is set to low. The

delay for power-on reset and the maximum permitted watchdog-pulse period can be set

externally with a capacitor.

Design Notes for External Components

An input capacitor

I is necessary for compensation of line influences. The resonant

circuit consisting of lead inductance and input capacitance can be damped by a resistor

of approx. 1

Ω in series with C

I. An output capacitor CQ is necessary for the stability of

the regulating circuit. Stability is guaranteed at values of

Q ≥ 22 µF and an ESR of

Ω.

Circuit Description

The control amplifier compares a reference voltage, which is kept highly accurate by

resistance adjustment, to a voltage that is proportional to the output voltage and drives

the base of a series transistor via a buffer. Saturation control as a function of the load

current prevents any over-saturation of the power element.

If the output voltage decreases below 4.5 V, an external capacitor

D on pin 4 (D) will be

discharged by the reset generator. If the voltage on this capacitor

D drops below VDRL,

a reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage

rises above 4.5 V,

D will be charged with constant current. After the power-on-reset time

D reaches VDU and the reset output will be set high again. The value of the power-on-

reset time can be set within a wide range depending on the capacity of

D. The value of

the pull-up resistor at reset output is typically 30 k

Ω.

After

D has reached the voltage VDU and reset was set to high, the watchdog circuit is

enabled and discharges

D with a constant current. If there is no positive-going edge

observed at watchdog input,

D will be discharged down to VDWL. Then reset will be set

low and the watchdog circuit will be disabled.

D will be charged with the current as at

power-on reset until

D reaches VDU and reset will be set high again.

If a watchdog pulse will be observed before

D is discharged down to VDWL, the watchdog

circuit will be enabled and

D will be charged too, but reset will not be set low. After VD

has reached

DU, the periodical behavior starts again.

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