D602

3V, 6GHz Divide-by-2 Static Prescaler

Final

Pin Out Diagram

In

Out

Out

In

V

EE

V

EE

PWD

V

CC

D602

1

2

3

4

8

7

6

5

Pin Out Description

Pin No.

Name

Description

1

Power Supply Voltage Input

2

In

Prescaler Input (internally-biased)

3

In

Prescaler Complementary Input (internally-biased)

4

Ground for Input (pins 4 and 5 must be connected to the same potential)

5

Ground for Output (pins 4 and 5 must be connected to the same potential)

6

Out

Complementary Output (open-collector)

7

Out

Output (open-collector)

8

PWD

Power Down high impedance CMOS input. When PWD is high, the part is powered

down.

Absolute Maximum Ratings

Operation in excess of any one of above Absolute Maximum Ratings may result in permanent damage. This device is

a high performance RF integrated and is ESD sensitive. The RF inputs on this device are Class 0 ESD rated;

therefore suitable precaution should be taken during handling, assembly and testing.

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

-0.3

+4.3

V

-0.3

V

Differential input voltage

-2.0

+2.0

V

Storage Temperature

-65

+150

°C

20-DST-01 Rev 5.0 Sept/01

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