SP2209E datasheet(10/15 Pages) SIPEX

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SP2209E DS/06

SP2209E High ESD Dual Port RS-232 Transceivers

ESD Tolerance

The SP2209E device incorporates ruggedized

ESD cells on all driver output and receiver input

pins. The ESD structure is improved over our

previous family for more rugged applications

and environments sensitive to electro-static

Phase 1

— V

DD charge storage — S1 and S2 are closed.

S3 and S4 are open. During this phase of the

clock cycle, the positive side of capacitor, C1, is

connected to V

DD. The negative side of C1 is

connected to GND. C1 is charged to +V

DD.

Phase 2

— V

DD transfer — S1 and S2 are open. S3 and

S4 are closed. The negative side of the capacitor,

C2, is connected to C2-. The positive side of C2

is connected to GND. This transfers a negative

generated voltage to C2. A negative voltage is

built up on the negative side of C2 with each

cycle of the oscillator. If the current drawn is

small, the output voltage at C2- will be close to

-V

DD. As the current drawn at C2- increases, the

output voltage will decrease in magnitude. The

charge pump cycle will continue as long as the

operational conditions for the internal oscillator

are present. Refer to Figure 8 for the internal

charge pump waveforms.

Standby Circuitry

The SP2209E device incorporates power

saving, on board standby circuitry. The standby

current is typically less than 100

µA.

The SP2209E device automatically enters a

standby mode when the V

DD power supply is

removed. An internal comparator generates an

internal shutdown signal that disables the

internal oscillator disengaging the charge pump.

Refer to Figure 9 for the internal standby

detection circuit.

The inverted output V- goes to ground. All

driver outputs are disabled. The inputs of

receivers 1 through 4 for both ports A and B are

at high impedance. Receiver 5 for both ports A

and B remain fully active as power management

receiver lines to system peripherals that may

come online during the standby mode.

VDD

VSTBY

Internal

Shutdown

Signal

Figure 9. Internal Standby Detection Circuit

discharges and associated transients. The

improved ESD tolerance is at least +15kV

without damage nor latch-up.

There are different methods of ESD testing

applied:

a) MIL-STD-883, Method 3015.7

b) EN61000-4-2 Air-Discharge

c) EN61000-4-2 Direct Contact

The Human Body Model has been the generally

accepted ESD testing method for semiconductors.

This method is also specified in MIL-STD-883,

Method 3015.7 for ESD testing. The premise of

this ESD test is to simulate the human body’s

potential to store electro-static energy and

discharge it to an integrated circuit. The

simulation is performed by using a test model as

shown in Figure 10. This method will test the

IC’s capability to withstand an ESD transient

during normal handling such as in manufacturing

areas where the ICs tend to be handled frequently.

The EN61000-4-2, formerly IEC801-2, is

generally used for testing ESD on equipment and

systems. For system manufacturers, they must

guarantee a certain amount of ESD protection

since the system itself is exposed to the outside

environment and human presence. The premise

with EN61000-4-2 is that the system is required

to withstand an amount of static electricity when

ESD is applied to points and surfaces of the

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