SP8542/8544DS/01

SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's

© Copyright 2000 Sipex Corporation

9

TIMING CHARACTERISTICS

(Typical @ 25

°C with V

PARAMETER

MIN.

TYP.

MAX.

UNIT

COND.

Thoughput Time (tTP=tA+tC)

4.25

µs

Acquisition Time (tA) (2 SCLK Periods)

400

500

ns

Conversion Time (tC) (15 SCLK Periods)

3.75

µs

SCLKLow Pulse Width (tSKL)

110

125

ns

SCLK High Pulse Width (tSKH)

110

125

ns

SCLK Period (tSKT)

250

ns

Setup Time DIN to SCLK Rising (tDISU)

0

ns

Hold Time from SCLK Rising to DIN (tDIH).

5

ns

Buss Relinquish Time (tBR)

45

ns

Setup Time -SCLK Falling to CSN Falling (tCSSU)

10

ns

CSN Low Before SCLK Rises (tCS)

90

ns

SCLK Falling to Data Valid (tSD)

50

ns

CSN Falling to STATUS Rising (tDCS)

69

ns

SCLK 17Falling to Status Rising Free Run (tDSS)

70

ns

SCLK16 Falling to Status Falling ( tDSE)

45

ns

Delay SD Low to initiate Conversion (t

µs

Aperture Delay Slave-Mode (tAPC)

30

ns

Aperture Delay Free-Running Mode (tAPS)

35

ns