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SL4017BD Datasheet(PDF) 5 Page - System Logic Semiconductor |
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SL4017BD Datasheet(HTML) 5 Page - System Logic Semiconductor |
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5 / 8 page  SL4017B System Logic Semiconductor SL S AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kΩ, Input tr=tf=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥ -55°C 25°C ≤ 125° C Unit fmax Maximum Clock Frequency 5.0 10 15 2.5 5 5.5 2.5 5 5.5 1.25 2.5 2.75 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Decode Output (Figure 1) 5.0 10 15 650 270 170 650 270 170 1300 540 340 ns tPLH, tPHL Maximum Propagation Delay, Clock to Carry Output (Figure 1) 5.0 10 15 600 250 160 600 250 160 1200 500 320 ns tTLH, tTHL Maximum Output Transition Time, Carry Output or Decode Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns tPLH, tPHL Maximum Propagation Delay, Reset to Carry Output or Decode Output (Figure 1) 5.0 10 15 530 230 170 530 230 170 1060 460 340 ns CIN Maximum Input Capacitance - 5 pF TIMING REQUIREMENTS (VCC=5.0V±10%, CL=50pF, Input tr=tf=20 ns, RL=200kΩ ) VCC Guaranteed Limit Symbol Parameter V ≥ -55°C 25°C ≤ 125° C Unit tw Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 200 90 60 200 90 60 400 180 120 ns tr, tf Maximum Input Rise and Fall Times, Clock (Figure 1) 5.0 10 15 UNLIMITED µ s tw Minimum Pulse Width, Reset (Figure 1) 5.0 10 15 260 110 60 260 110 60 520 220 120 ns trem Minimum Removal Time, Reset (Figure 1) 5.0 10 15 400 280 150 400 280 150 800 560 300 ns |
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