CY29352

Document Number: 38-07476 Rev. *C

Page 2 of 10

Pinouts

Figure 1. Pin Diagram - 32-pin 1.4 mm TQFP package

CY29352

VSS

QB1

QB0

VDDQB

VDDQA

QA4

QA3

VSS

VCO_SEL

SELC

SELB

SELA

MR/OE#

REFCLK

AVSS

FB_IN

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

Notes

1. PD = Internal pull down.

2. A 0.1-

F bypass capacitor must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, the high

frequency filtering characteristics are cancelled by the lead inductance of the traces.

Table 1. Pin Definition - 32-pin 1.4 mm TQFP package

Pin

Name

IO[1]

Type

Description

6

REFCLK

I, PD

LVCMOS

Reference clock input

12, 14, 15, 18, 19 QA(0:4)

O

LVCMOS

Clock output bank A

22, 23, 26, 27

QB(0:3)

O

LVCMOS

Clock output bank B

30, 31

QC(0,1)

O

LVCMOS

Clock output bank C

8

FB_IN

I, PD

LVCMOS

Feedback clock input. Connect to an output for normal operation. This

input must be at the same voltage rail as input reference clock, see

Table 2 on page 3.

1

VCO_SEL

I, PD

LVCMOS

VCO divider select input, see Table 3 on page 3.

5

MR/OE#

I, PD

LVCMOS

Master reset or output enable and disable input, see Table 3 on page 3.

9

PLL_EN#

I, PD

LVCMOS

PLL enable and disable input, see Table 3 on page 3.

2, 3, 4

SEL(A:C)

I, PD

LVCMOS

Frequency select input, bank (A:C), see Table 3 on page 3.

16, 20

Supply

2.5 V or 3.3 V power supply for bank A output clocks [2,3]

21, 25

Supply

2.5 V or 3.3 V power supply for bank B output clocks [2,3]

32

Supply

2.5 V or 3.3 V power supply for bank C output clocks [2,3]

10

Supply

2.5 V or 3.3 V power supply for PLL [2,3]

11

Supply

2.5 V or 3.3 V power supply for core and inputs [2,3]

Supply

Ground

Analog ground

Supply

Ground

Common ground

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