DAC902 datasheet(11/24 Pages) TI1

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DAC902

SBAS094B

APPLICATION INFORMATION

THEORY OF OPERATION

The architecture of the DAC902 uses the current steering

technique to enable fast switching and a high update rate. The

core element within the monolithic DAC is an array of

segmented current sources that are designed to deliver a full-

scale output current of up to 20mA, as shown in Figure 1. An

internal decoder addresses the differential current switches

each time the DAC is updated and a corresponding output

current is formed by steering all currents to either output

summing node, IOUT or IOUT. The complementary outputs

deliver a differential output signal that improves the dynamic

performance through reduction of even-order harmonics,

common-mode signals (noise), and double the peak-to-peak

output signal swing by a factor of two, compared to single-

ended operation.

The segmented architecture results in a significant reduc-

tion of the glitch energy, improves the dynamic perfor-

mance (SFDR), and DNL. The current outputs maintain a

very high output impedance of greater than 200k

Ω.

The full-scale output current is determined by the ratio of

the internal reference voltage (1.24V) and an external

resistor, RSET. The resulting IREF is internally multiplied by

a factor of 32 to produce an effective DAC output current

that can range from 2mA to 20mA, depending on the value

of RSET.

The DAC902 is split into a digital and an analog portion,

each of which is powered through its own supply pin. The

digital section includes edge-triggered input latches and the

decoder logic, while the analog section comprises the cur-

rent source array with its associated switches, and the

reference circuitry.

DAC TRANSFER FUNCTION

The total output current, IOUTFS, of the DAC902 is the

summation of the two complementary output currents:

IOUTFS = IOUT + IOUT

(1)

The individual output currents depend on the DAC code and

can be expressed as:

IOUT = IOUTFS • (Code/4096)

(2)

IOUT = IOUTFS • (4095 – Code/4096)

(3)

where ‘Code’ is the decimal representation of the DAC data

input word. Additionally, IOUTFS is a function of the refer-

ence current IREF, which is determined by the reference

voltage and the external setting resistor, RSET.

IOUTFS = 32 • IREF = 32 • VREF/RSET

(4)

In most cases the complementary outputs will drive resistive

loads or a terminated transformer. A signal voltage will

develop at each output according to:

VOUT = IOUT • RLOAD

(5)

VOUT = IOUT • RLOAD

(6)

FIGURE 1. Functional Block Diagram of the DAC902.

PMOS

Current

Source

Array

LSB

Switches

Segmented

MSB

Switches

+1.24V Ref

Latches and Switch

Decoder Logic

12-Bit Data Input

D11...D0

DAC902

Full-Scale

Adjust

Resistor

Ref

Control

Amp

Ref

Buffer

SET

Ω

CLK

DGND

Ref

Input

0.1

µF

INT/EXT

OUT

BYP

20pF

Ω

20pF

1:1

OUT

0.1

µF

400pF

0.1

µF

+3V to +5V

Analog

Bandwidth

Control

+3V to +5V

Digital

FSA

REF

AGND

Analog

Ground

Digital

Ground

Power Down

(internal pull-down)

Clock

Input

NOTE: Supply bypassing not shown.

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