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SL74HC192 Datasheet(PDF) 4 Page - System Logic Semiconductor

Part # SL74HC192
Description  Presettable BCD/Decade UP/DOWN Counter
PDF  7 Pages
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Manufacturer  SLS [System Logic Semiconductor]
Direct Link  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL74HC192 Datasheet(HTML) 4 Page - System Logic Semiconductor

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SL74HC192
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
fmax
Minimum Clock Frequency (50% Duty Cycle)
(Figures 1 and 6)
2.0
4.5
6.0
12
36
43
3.2
16
19
2.6
13
15
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q (Figures
1 and 6)
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
ns
tPLH, tPHL
Maximum Propagation Delay, PL to Q
(Figures 3 and 6)
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
ns
tPLH, tPHL
Maximum Propagation Delay, Clock to Terminal
Count (Figures 2 and 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH, tTHL
Maximum Output Transition Time,Any Output
(Figures 1 and 6)
2.0
4.5
6.0
75
15
13
95
20
18
110
23
20
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
Typical @25
°C,V
CC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC
2f+I
CCVCC
60
pF
TIMING REQUIREMENTS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to -55°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Pn to PL
(Figure 4)
2.0
4.5
6.0
100
20
18
125
35
22
150
30
26
ns
th
Minimum Hold Time, Pn to PL (Figure
4)
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
tw
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tw
Minimum Pulse Width, PL
(Figure 3)
2.0
4.5
6.0
100
20
17
125
25
26
150
30
26
ns
tw
Minimum Pulse Width, MR
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
26
150
30
26
ns
tr, tf
Minimum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
100
500
400
100
500
400
100
500
400
ns



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