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SL74HC4046 Datasheet(PDF) 3 Page - System Logic Semiconductor

Part # SL74HC4046
Description  Phase-Locked Loop
PDF  12 Pages
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Manufacturer  SLS [System Logic Semiconductor]
Direct Link  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL74HC4046 Datasheet(HTML) 3 Page - System Logic Semiconductor

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SL74HC4046
System Logic
Semiconductor
SLS
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
°C
to
-55
°C
≤85
°C
≤125
°C
Unit
VIH
Minimum High-Level
Input Voltage DC
Coupled
SIGIN , COMPIN
VOUT= 0.1 V or VCC-0.1 V
I
OUT
≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low -Level
Input Voltage DC
Coupled
SIGIN , COMPIN
VOUT=0.1 V or VCC-0.1 V
I
OUT
 ≤ 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum High-Level
Output Voltage
PCPOUT, PCnOUT
VIN=VIH or VIL
I
OUT
 ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN= VIH or VIL
I
OUT
 ≤ 4.0 mA
I
OUT
 ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-Level
Output Voltage Qa-Qh
PCPOUT, PCnOUT
VIN=VIH or VIL
I
OUT
 ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIH or VIL
I
OUT
 ≤ 4.0 mA
I
OUT
 ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
SIGIN , COMPIN
VIN=VCC or GND
2.0
3.0
4.5
6.0
±3.0
±7.0
±18.0
±30.0
±4.0
±9.0
±23.0
±38.0
±5.0
±11.0
±27.0
±45.0
µA
IOZ
Maximum Three-State
Leakage Current
PC2OUT
Output in High-Impedance
State
VIN= VIL or VIH
VOUT=VCC or GND
6.0
±0.5
±5.0
±10
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
(VCO disabled)
Pins 3,5 and 14 at VCC
Pin 9 at GND; Input
Leacage at
Pin 3 and 14 to be
excluded
VIN=VCC or GND
IOUT=0
µA
6.0
4.0
40
160
µA



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