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74ACT11478 Datasheet(PDF) 1 Page - Texas Instruments

Part # 74ACT11478
Description  METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP WITH 3-STATE OUTPUTS
PDF  5 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

74ACT11478 Datasheet(HTML) 1 Page - Texas Instruments

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74ACT11478
METASTABLERESISTAND OCTAL DTYPE DUALRANK FLIPFLOP
WITH 3-STATE OUTPUTS
SCAS131 − APRIL 1990 − REVISED APRIL 1993
Copyright
1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
• Inputs Are TTL-Voltage Compatible
• Specifically Designed for Data
Synchronization Applications
• Improved Metastable Characteristics
Provide Greater System Reliability
• 3-State Outputs Drive Bus Lines Directly
• Flow-Through Architecture to Optimize
PCB Layout
• Center-Pin V
CC and GND Configurations to
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
CMOS) 1-
mm Process
• 500-mA Typical Latch-Up Immunity
at 125
°C
• Package Options Include Plastic Small
Outline Packages and Standard Plastic
300-mil DIPs
description
The 74ACT11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization
applications where the normal setup and hold time specifications are frequently violated.
Synchronization of two digital signals operating at different frequencies is a common system problem. This
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the
setup or hold time specification is violated, the output response is uncertain.
A flip-flop is metastable if its output hangs up in the region between VIL and VIH. The metastable condition lasts
until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can
be longer than the specified maximum propagation delay.
The problem of metastability is typically solved by adding an additional layer of synchronization. This type of
dual ranking is employed in the 74ACT11478. The probability of the second stage entering the metastable state
is exponentially reduced by this dual-rank architecture. The 74ACT11478 provides a one-chip solution for
system designers in asynchronous applications.
The 74ACT11478 is characterized for operation from − 40
°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE
CLOCK†
D
Q
H
X
X
Z
L
↑
LL
L
↑
HH
L
H
X
QO
† Data presented at the D input requires two
clock cycles to appear at the Q output.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
OE
1D
2D
3D
4D
VCC
VCC
5D
6D
7D
8D
CLK
DW OR NT PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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