74ACT11656

OCTAL BUFFER/LINE DRIVER

WITH PARITY CHECKER/GENERATOR AND 3STATE OUTPUTS

SCAS460A − DECEMBER 1994 − REVISED APRIL 1996

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

One Package

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

µm Process

125

°C

description

The 74ACT11656 contains eight noninverting

buffers with 3-state outputs and a 9-bit parity

generator/checker. The device is intended for

bus-oriented applications.

When data is transmitted, the parity input (PI) terminal is configured as an input and combined with the A-input

data to generate a flag on either parity output (

ΣE or ΣO) terminal, depending on the number of inputs that are

high.

The output-enable (OE1, OE2, and OE3) inputs can be used to disable the device so that the buses are

effectively isolated.

The 74ACT11656 is characterized for operation from −40

°C to 85°C.

FUNCTION TABLES

INPUTS

OUTPUT

OE1

OE2

OE3

A

OUTPUT

Y

L

L

L

L

L

L

LL

H

H

H

XX

X

Z

X

HX

X

Z

X

X

H

X

Z

NO. OF INPUTS HIGH

(PI, A1−A8)

PARITY

OUTPUTS

(PI, A1−A8)

ΣE

ΣO

EVEN 0, 2, 4, 6, 8

H

L

ODD 1, 3, 5, 7, 9

L

H

Any OE = high

Z

Z

Copyright

 1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

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15

Y1

Y2

Y3

Y4

Y5

GND

GND

GND

GND

Y6

Y7

Y8

ΣE

ΣO

OE1

OE2

OE3

A1

A2

A3

A4

A5

A6

A7

A8

PI

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