74ACT11657

OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER

AND 3STATE OUTPUTS

SCAS232 − AUGUST 1992 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Copyright

2−1

PCB Layout

Configurations Minimize High-Speed

Switching Noise

CMOS) 1-

µm Process

at 125

°C

Small-Outline Packages and Standard

Plastic 300-mil DIPs

description

The 74ACT11657 contains eight noninverting

buffers with 3-state outputs and an 8-bit parity

generator/checker and is intended for bus-

oriented applications.

The transmit/receive (T/R) input determines the direction of data flow through the bidirectional transceivers.

When T/R is high, data flows from the A port to the B port (transmit mode); when T/R is low, data flows from

the B port to the A port (receive mode). When the output-enable (OE) input is high, both the A and B ports are

in the high-impedance state.

Odd or even parity is selected by a logic high or low level, respectively, on the ODD/EVEN input. PARITY carries

the parity bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity

generator/checker in the receive mode.

In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic

level that maintains the parity sense selected by the level at the ODD/EVEN input. For example, if ODD/EVEN

is low (even parity selected) and there are five high bits on the A bus, then PARITY is set to the logic high level

so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.

In the receive mode, after the B bus is polled to determine the number of high bits, the ERR output logic level

indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN

is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, then ERR is low,

indicating a parity error.

The 74ACT11657 is characterized for operation from − 40

°C to 85°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.

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PARITY

A1

A2

A3

A4

GND

GND

GND

GND

A5

A6

A7

A8

ERR

OE

B1

B2

B3

B4

B5

B6

B7

B8

ODD/EVEN

T/R

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