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74HC4094 Datasheet(PDF) 4 Page - System Logic Semiconductor

Part # 74HC4094
Description  8-Bit Serial-Input Shift Register With Latched 3-State Outputs(High-Performance Silicon-Gate CMOS)
PDF  7 Pages
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Manufacturer  SLS [System Logic Semiconductor]
Direct Link  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

74HC4094 Datasheet(HTML) 4 Page - System Logic Semiconductor

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SL74HC4094
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
6
30
35
5
25
28
4
20
23
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to SQH
(Figures 1 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPLH, tPHL
Maximum Propagation Delay, Clock to QA-QH
(Figures 2 and 5)
2.0
4.5
6.0
195
40
33
245
50
42
295
60
50
ns
tPLZ, tPHZ
Maximum Propagation Delay ,Output Enable to
QA-QH (Figures 3 and 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tPZL, tPZH
Maximu m Propagation Delay ,Output Enable to
QA-QH (Figures 3 and 6)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State), QA-QH
-
15
15
15
pF
Power Dissipation Capacitance (Per Package)
Typical @25
°C,V
CC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC
2f+I
CCVCC
300
pF
TIMING REQUIREMENTS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Serial Data
Input A to Clock (Figure 4)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
th
Minimum Hold Time, Clock to Data
Input A (Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
tw
Minimum Pulse Width, Strobe (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns



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