PC34709VK datasheet(39/142 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

34709

Functional Block Description

7.5.3.8

Power Saving

7.5.3.8.1

System Standby

A product may be designed to enter DSM after periods of inactivity, the STANDBY pin is provided for board level control of timing

in and out of such deep sleep modes.

When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing

the operating mode of the switching regulators, or disabling some regulators. This can be obtained by controlling the STANDBY

pin. The configuration of the regulators in standby is pre-programmed through the SPI.

A lower power standby mode can be obtained by setting the ON_STBY_LP SPI bit to a one. With the ON_STBY_LP SPI bit set

and the STANDBY pin asserted, a lower power standby will be entered. In the on Standby Low-power mode, the switching

Regulators should all be programmed into PFM mode, and the LDO's should be configured to Low-power mode when the

STANDBY pin is asserted. The PLL is disabled in this mode

Note that the STANDBY pin is programmable for Active High or Active Low polarity, and the decoding of a Standby event will

take into account the programmed input polarity associated with each pin. For simplicity, Standby will generally be referred to as

active high throughout this document, but as defined in Table 26, active low operation can be accommodated. Finally, since the

STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond

to the pin level changes.

The state of the STANDBY pin only has influence in On mode, and are therefore it is ignored during start-up and in the Watchdog

phase. This allows the system to power-up without concern of the required Standby polarities since software can make

adjustments accordingly as soon as it is running.

A command to transition to one of the low-power Off states (User Off or Memory Hold, initiated with USE-ROFFSPI=1) redefines

the power tree configuration based on SWxMODE programming, and has priority over Standby (which also influences the power

tree configuration).

7.5.3.8.2

Standby Delay

A provision to delay the Standby response is included. This allows the processor and peripherals, some time after a Standby

instruction has been received, to terminate processes to facilitate seamless Standby exiting and re-entrance into Normal

operating mode.

A programmable delay is provided to hold off the system response to a Standby event. When enabled (STBYDLY = 01, 10, or

11), STBYDLY will delay the STANDBY initiated response for the entire IC until the STBYDLY counter expires.

Table 25. VBATTDB Debounce Times

VATTDB[1:0]

Debounce Time (ms)

0.1

1.0

2.5

11 (default)

3.9

Table 26. Standby Pin and Polarity Control

STANDBY (Pin)

STANDBYINV (SPI bit)

STANDBY Control(37)

Notes

37.

STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby

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