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CDCLVP2106RHAT Datasheet(PDF) 1 Page - Texas Instruments

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Part # CDCLVP2106RHAT
Description  12 LVPECL Output, High-Performance Clock Buffer
PDF  23 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCLVP2106RHAT Datasheet(HTML) 1 Page - Texas Instruments

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LVPECL
6
6
2
Reference
Generator
GND
GND
OUTP[11...6]
OUTN[11...6]
LVPECL
6
6
OUTP[5...0]
OUTN[5...0]
V
CC
V
AC_REF[1, 0]
V
CC
V
CC
V
CC
V
CC
V
CC
INP0
INN0
INP1
INN1
CDCLVP2106
www.ti.com
SCAS887A
– SEPTEMBER 2009 – REVISED AUGUST 2011
12 LVPECL Output, High-Performance Clock Buffer
Check for Samples: CDCLVP2106
1
FEATURES
DESCRIPTION
The CDCLVP2106 is a highly versatile, low additive
2
•
Dual 1:6 Differential Buffer
jitter buffer that can generate 12 copies of LVPECL
•
Two Clock Inputs
clock outputs from two LVPECL, LVDS, or LVCMOS
•
Universal Inputs Can Accept LVPECL, LVDS,
inputs for a variety of communication applications. It
LVCMOS/LVTTL
has a maximum clock frequency up to 2 GHz. Each
buffer block consists of one input that feeds two
•
12 LVPECL Outputs
LVPECL
outputs.
The
overall
additive
jitter
•
Maximum Clock Frequency: 2 GHz
performance is less than 0.1 ps, RMS from 10 kHz to
•
Maximum Core Current Consumption: 92 mA
20 MHz, and overall output skew is as low as 20 ps,
making the device a perfect choice for use in
•
Very Low Additive Jitter:
<100 fs,rms in 10-kHz
demanding applications.
to 20-MHz Offset Range
The CDCLVP2106 clock buffer distributes two clock
•
2.375-V to 3.6-V Device Power Supply
inputs (IN0, IN1) to 12 pairs of differential LVPECL
•
Maximum Propagation Delay: 550 ps
clock outputs (OUT0, OUT11) with minimum skew for
•
Maximum Within Bank Output Skew: 20 ps
clock distribution. Each buffer block consists of one
•
LVPECL Reference Voltage, VAC_REF, Available
input that feeds two LVPECL clock outputs. The
inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
for Capacitive-Coupled Inputs
•
Industrial Temperature Range:
–40°C to +85°C
The CDCLVP2106 is specifically designed for driving
50-
Ω transmission lines. When driving the inputs in
•
Available in 6-mm
× 6-mm QFN-40 (RHA)
single-ended
mode,
the
LVPECL
bias
voltage
Package
(VAC_REF) should be applied to the unused negative
•
ESD Protection Exceeds 2 kV (HBM)
input pin. However, for high-speed performance up to
2 GHz, differential mode is strongly recommended.
APPLICATIONS
The CDCLVP2106 is characterized for operation
•
Wireless Communications
from
–40°C to +85°C and is available in a QFN-40,
•
Telecommunications/Networking
6-mm
× 6-mm package.
•
Medical Imaging
•
Test and Measurement Equipment
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright
© 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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