Executive functions allow preemption to be selectively

turned on or off by task or for an entire application

224 Time Slicing

Time slicing modifies the task scheduling algorithm as fol-

lows at each ‘‘tick’’ of the timer clock (the clock which also

controls the time-out timers) if the currently running task

has the same priority as the task at the head of the Ready

Queue then if the currently running task is not in a non-pre-

empt section it will stop running and the task at the head of

the Ready Queue will run The task that stops running is

placed on the Ready Queue in the normal manner ie after

all tasks of equal priority Time slicing enables the Executive

to share the processor equally between tasks of equal prior-

ity

225 Mailboxes and Mail Messages

The main form of intertask communication is the sending

and receiving of mail Mailboxes exist independently of

tasks any task may send mail to any mailbox and any task

may read mail from any mailbox However in a typical sys-

tem each task has one mailbox from which it reads all its

mail and to which other tasks send mail destined for that

task

Mail is prioritized When a task calls upon the Executive to

perform a SendMail it specifies the priority of the message

which is inserted in the specified mailbox queue sorted by

priority

226 Timers

The Executive includes a timing facility specifically designed

to handle the time-outs typical of telecom protocols and oth-

er real-time applications

Timers are essentially a form of delayed mail When a task

sets a timer the task provides a mailbox identifier a mail

message and a time delay value When the specified time

delay is up ie when the timer ‘‘expires’’ the mail message

is mailed to the specified mailbox When a task sets a timer

it receives a timer ID which can be used to cancel the timer

if necessary before it expires

227 Memory Management

The memory manager is responsible for allocating and deal-

locating fixed-size memory blocks from fixed-size pools

which are completely defined at compile time A memory

pool may reside in extended memory

228 System Module and Interface Module

The Multi-Tasking Executive Software is available either as

source code or as object code The interface module which

must be modified to insert application tasks is always sup-

plied as source code

23 IO DEVICE DRIVERS

IO Device Drivers serve as interface routines between the

HPC hardware machinery and the HPC Executive and Appli-

cation Tasks ‘‘Input’’ operations (data heading toward Ap-

plication Tasks) are typically fielded by an Interrupt Service

Routine (ISR) The ISR may SEND information to the appro-

priate task via the system mail facility or it may signal the

appropriate semaphore to schedule an IO task ‘‘Output’’

operations (data heading away from Application Tasks) are

typically fielded by Service Request (SRQ) Tasks SRQ

Tasks communicate directly with the hardware control regis-

ters to initiate output operations These tasks often work

closely with their accompanying ISR for output initiation and

completion Higher layer tasks send mail messages to he

SRQ Tasks using the system mail facility to queue mes-

sages pending output

The HPC ISDN Software includes three IO Device Drivers

the Layer 1 Driver the Layer 2 Driver and the Terminal Driv-

er The functionality of these drivers is defined below De-

tails of particular Device Driver ISR and SRQ Task interac-

tions are defined in the Software User’s Manual

231 Layer 1 IO Device Driver

The Layer 1 IO Device Driver provides implementation of

the ISDN PHYSICAL Layer 1 for the HPC environment This

Device Driver controls the NSC MICROWIREPLUS Inter-

face to the NSC TP3420 ‘‘S’’ Interface Device (SID) and

the HPC16400 onboard

Serial Decoder

Control of a

mented later by either adding to this driver or using it as a

model for additional drivers

The primary responsibility of this driver is to initialize and

control the SID The higher layer ISDN tasks mail activation

and deactivation messages to the Layer 1 Service Request

Task This task sends the appropriate command to the SID

via the MICROWIREPLUS Interface The SID interrupts the

HPC whenever it changes state The Layer 1 Interrupt Serv-

ice Routine fields responses when the SID changes state

and mails the information to the Layer 2 Controller Task and

to the Management Entity Task

The Serial Decoder is initialized to MODE 4 with the ISDN D

Channel terminated by DMAHDLC Channel

1 and Bear-

er Channel B2 terminated by DMAHDLC Channel

2 The

SID can swap B1 and B2 internally to allow voice or data on

either channel

The Layer 1 IO Device Driver can communicate with any

other Task via the System Mail Utilities

232 Layer 2 IO Device Driver

The Layer 2 IO Device Driver interfaces the two HPC16400

onboard DMAHDLC channels one to the 16 kbit per sec-

ond ‘‘D’’ signaling channel and one to the 64 kbit per sec-

ond bearer (B2) channel The Layer 2 Service Request Task

receives Physical Layer (PH) Primitives from the Layer 2

Controller Task via the system mail utility The Layer 2 Inter-

rupt Service Routine handles block messages received from

the DMA Controller and mails them as Physical Layer (PH)

Data Primitives to the Layer 2 Controller Task This generic

mail message interface allows an Application User to easily

introduce external DMA and HDLC Controllers and accom-

panying device drivers that either replace or complement

the existing onboard controllers

HDLCDMA Channel

1 is attached to the ISDN signaling

D channel and will be referred to as the LAPD Channel

HDLCDMA Channel

2 is attached to bearer channel B2

and will be referred to as the LAPB Channel The two chan-

nels operate independently of each other as much as possi-

ble Since they share the same interrupt hardware the Lay-

er 2 Interrupt Service Routine must poll the Message Pend-

ing Register and the Error Status Register to determine the

source of each interrupt Both HDLCDMA channels use

the HPC field separation feature for transmission and recep-

tion of data This feature relieves some memory concerns

since it allows small memory buffers to be used for mes-

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