MPT57202

160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN

SGLS093 – MARCH 1997

2

POST OFFICE BOX 655303

function table

SIGNAL

COMMON (ROW) MODE

BS

Not Used (tie low)

D7-D0

Not Used (tie low)

DISP OFF†

TEST VL2 (display off): L

DST

Data shift on falling edge

80 CH

L = 160-channel

H=80-channel x 2 (parallel)

EIO1

Serial I/O

1 CH Serial I/O

EIO2

See Note 1

80 CH Serial I/O

EIO3

See Note 1

81 CH Serial I/O

EIO4

Serial I/O

160 CH Serial I/O

L/R = L (left shift)

L/R = L (left shift)

EIO1

← <R1> ← <R2> ← <R3>...← <R160> ← EIO4

EIO1

← <R1> ← <R2> ← <R3>...← <R160> ← EIO4

L/R = H (right shift)

L/R

L/R = H (right shift)

EIO1

→ <R1> → <R2> → <R3>...→ <R160> → EIO4

L/R

EIO1

→ <R1> → <R2> → <R3>...→ <R160> → EIO4

M, data combination

Selects level

0,1

VL1

,

1,0

VL3

M

0,0

11

VL4

VL2

1,1

VL2

MODE

L

SCK

Not used (tie low)

TEST

Test pin = L or open

† This terminal should be low at power up for logic resetting.

NOTE 1: This terminal is not used in this configuration. Although the pin produces a low output level, it should be left open.