THS8200IPFPEP datasheet(71/104 Pages) TI1

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THS8200-EP

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SLES253 – DECEMBER 2009

{tst_cntl2 0x1B(7:6)}

[00]

Adjusts the delay of the Y channel during YCbCr modes

tst_fastramp:

DAC test control, fast ramp

{tst_cntl2 0x1B(1)}

[0]

0 : Normal operation

1 : DAC outputs a ramp at 2× clock rate.

tst_slowramp:

DAC test control, slow ramp

{tst_cntl2 0x1B(0)}

[0]

0 : Normal operation

1 : DAC outputs a ramp at 2× clock rate divided by 64,000. This mode has a higher priority than the

one set by tst_fastramp

5.1.4

Data Path Control (Sub-Address 0x1C)

data_clk656_on:

ITU-R.BT656 output clock control

{data_cntl 0x1C(7)}

[0]

0 : D1CLKO output off

1 : D1CLKO output on

data_fsadj:

Full-scale adjust control

{data_cntl 0x1C(6)}

[0]

Selects which full-scale setting to use. See FSADJ<n> terminal description for nominal full-scale

adjust resistor values.

0 : Use full-scale setting from resistor connected to FSADJ2 terminal

1 : Use full-scale setting from resistor connected to FSADJ1 terminal

data_ifir12_bypass:

Bypass control 4:2:2 to 4:4:4

{data_cntl 0x1C(5)}

[0]

0 : Interpolation filters before the CSC are in the data path, enabling 4:2:2 to 4:4:4 conversion

internally. This mode should be used when the input data is in 4:2:2 format

1 : Interpolation filters before the CSC are bypassed. This mode should be used when the input data

is in 4:4:4 format.

data_ifir35_bypass:

Bypass control 2x interpolation

{data_cntl 0x1C(4)}

[0]

0 : interpolation filters after the CSC are in the data path; enabling 1× to 2× interpolation of the video

data.

1 : interpolation filters after the CSC are bypassed. This mode should be used when 1× DAC

operation is desired.

data_tristate656:

ITU-R.BT656 output bus

{data_cntl 0x1C(3)}

[0]

0 : the ITU-R.BT656 output bus is active.

1 : the ITU-R.BT656 output bus is in the high-impedance state.

I2C Register Map

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