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TMS570LS3135 Datasheet(PDF) 97 Page - Texas Instruments |
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TMS570LS3135 Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 154 page  TMS570LS2125 TMS570LS2135 TMS570LS3135 www.ti.com SPNS164 – SEPTEMBER 2011 Table 4-35. ESM Channel Assignments (continued) ERROR SOURCES GROUP CHANNELS MibSPI3 - parity Group1 18 MibADC1 - parity Group1 19 Reserved Group1 20 DCAN1 - parity Group1 21 DCAN3 - parity Group1 22 DCAN2 - parity Group1 23 MibSPI5 - parity Group1 24 Reserved Group1 25 RAM even bank (B0TCM) - correctable error Group1 26 CPU - selftest Group1 27 RAM odd bank (B1TCM) - correctable error Group1 28 Reserved Group1 29 DCC1 - error Group1 30 CCM-R4 - selftest Group1 31 Reserved Group1 32 Reserved Group1 33 Reserved Group1 34 FMC - correctable error (EEPROM bank access) Group1 35 FMC - uncorrectable error (EEPROM bank access) Group1 36 IOMM - Mux configuration error Group1 37 Power domain controller compare error Group1 38 Power domain controller self-test error Group1 39 eFuse Controller Error – this error signal is generated when any bit in the eFuse controller error status register is set. The application can choose to generate an Group1 40 interrupt whenever this bit is set to service any eFuse controller error conditions. eFuse Controller - Self Test Error. This error signal is generated only when a self test on the eFuse controller generates an error condition. When this error signal is Group1 41 set, group 1 channel 40 error signal will also be set. PLL2 - Slip Group1 42 Reserved Group1 43 Reserved Group1 44 Reserved Group1 45 Reserved Group1 46 Reserved Group1 47 Reserved Group1 48 Reserved Group1 49 Reserved Group1 50 Reserved Group1 51 Reserved Group1 52 Reserved Group1 53 Reserved Group1 54 Reserved Group1 55 Reserved Group1 56 Reserved Group1 57 Reserved Group1 58 Reserved Group1 59 Reserved Group1 60 Reserved Group1 61 Copyright © 2011, Texas Instruments Incorporated System Information and Electrical Specifications 97 Submit Documentation Feedback focus.ti.com: TMS570LS2125 TMS570LS2135 TMS570LS3135 |
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