TNETX3100PGC datasheet(70/80 Pages) TI1

70 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DIO read cycle

D TNETX3100 host-register address data is placed on address terminals SAD1–SAD0 and SRNW is held

high.

D After setup time, SCS is taken low, initiating the read cycle.

D After delay following SCS low, SDATA7–SDATA0 is released from the Z state.

D After delay following SCS low, SDATA7–SDATA0 is driven with valid data and SRDY is pulled low. The host

can access the data.

D SCS is taken high by the host upon completion of the cycle, causing SRDY to deassert, and SRDY is driven

high for one clock cycle before going to the Z state. SDATA7–SDATA0 also goes to the Z state.

timing requirements (see Note 12 and Figure 20)

read cycle DIO interface

NO.

MIN

MAX

UNIT

tw(SCS)

Pulse duration, SCS low

tsu(SAD)

Setup time, SAD1–SAD0 valid before SCS

↓

tsu(SRNW)

Setup time, SRNW high before SCS

↓

NOTE 12: SRDY should be held high using an external pullup resistor to ensure correct system operation.

operating characteristics over recommended operating conditions (see Note 12 and Figure 20)

read cycle DIO interface

NO.

PARAMETER

MIN

MAX

UNIT

tw(SRDY)

Pulse duration, SRDY high

td(SRNW)

Delay time, from SRDY

↓ to SRNW↓

td(SAD)

Delay time, from SRDY

↓ to SAD1–SAD0 invalid

td(SDATA)1

Delay time from SRDY

↓ to SDATA7–SDATA0 valid

td(SDATA)2

Delay time from SCS

↑ to SDATA7–SDATA0 invalid

td(SCS–SRDY)1

Delay time, SCS

↓ to SRDY↓

td(SCS–SRDY)2

Delay time, SCS

↑ to SRDY↑

NOTE 12: SRDY should be held high using an external pullup resistor to ensure correct system operation.

Address

Data

SCS

(input)

SRNW

(input)

SAD1–SAD0

(input)

SDATA7–SDATA0

(output)

SRDY

(output)

OSCIN

(input)

Figure 20. DIO Read Cycle

TNETX3100PGC Datasheet(PDF) 70 Page - Texas Instruments

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