TNETX3110 datasheet(52/65 Pages) TI1

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TNETX3110

ThunderSWITCH

™ 8/3 ETHERNET™ SWITCH

WITH 8 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS047A – MARCH 1998 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

10-Mbit/s interface (ports 00–07)

timing requirements (see Notes 3 through 6 and Figure 12)

NO.

MIN

MAX

UNIT

tc(TH2CLK)

Cycle time, TH2CLK

Tw(TH2CLK)

Pulse duration, TH2CLK high or low

tsu(TH2SYNC)

Setup time, TH2SYNC high before TH2CLK

↓

tsu(TH2COL)

Setup time, TH2COL high before TH2CLK

↑

tsu(TH2CRS)

Setup time, TH2CRS high before TH2CLK

↑

tsu(TH2LINK)

Setup time, TH2LINK high before TH2CLK

↑

tsu(TH2RXD)

Setup time, TH2RXD3–TH2RXD0 valid before TH2CLK

↑

tsu(TH2RXDV)

Setup time, TH2RXDV high before TH2CLK

↑

th(TH2SYNC)

Hold time, TH2SYNC high after TH2CLK

↓

th(TH2COL)

Hold time, TH2COL high after TH2CLK

↑

th(TH2CRS)

Hold time, TH2CRS high after TH2CLK

↑

th(TH2LINK)

Hold time, TH2LINK high after TH2CLK

↑

th(TH2RXD)

Hold time, TH2RXD3–TH2RXD0 valid after TH2CLK

↑

th(TH2RXV)

Hold time, TH2RXDV high after TH2CLK

↑

tr(TH2CLK)

Rise time, TH2CLK

tf(TH2CLK)

Fall time, TH2CLK

NOTES:

3. The TNETE2008 must supply at least two TH2SYNC pulses under normal conditions before driving valid data on the inputs to the

TNETX3110, or before expecting valid data on the outputs from the TNETX3110. This means that at least two full sequences must

be executed; only with the third TH2SYNC pulse is valid data presented/expected.

4. At least two clocks must be driven before the deassertion of the system reset signal, and a minimum of two clocks must be driven

after the deassertion of the the system reset signal to ensure complete initialization of the internal circuitry of the TNETX3110 before

there is any valid activity across the interface.

5. For receive data, the TNETE2008 asserts the TH2COL signal during the appropriate slot time if it was asserted for any of the four

bits of data corresponding to that slot time.

6. For receive data, the TNETE2008 asserts the TH2RXDV signal only if there are four valid bits of data in the nibble.

operating characteristics over recommended operating conditions (see Notes 3 through 6 and

Figure 12)

NO.

PARAMETER

MIN

MAX

UNIT

td(TH2EN)

Delay time, from TH2CLK

↑ to TH2TXEN↑

13.5

td(TH2TXD)

Delay time, from TH2CLK

↑ to TH2TXD3–TH2TXD0 valid

13.5

td(TH2RENEG)

Delay time, from TH2CLK

↑ to TH2RENEG↓

13.5

td(TH2TXEN)

Delay time, from TH2CLK

↑ to TH2TXEN↓

td(TH2TXD)

Delay time, from TH2CLK

↑ to TH2TXD3–TH2TXD0 invalid

td(TH2RENEG)

Delay time, from TH2CLK

↑ to TH2RENEG↑

NOTES:

3. The TNETE2008 must supply at least two TH2SYNC pulses under normal conditions before driving valid data on the inputs to the

TNETX3110, or before expecting valid data on the outputs from the TNETX3110. This means that at least two full sequences must

be executed; only with the third TH2SYNC pulse is valid data presented/expected.

4. At least two clocks must be driven before the deassertion of the system reset signal, and a minimum of two clocks must be driven

after the deassertion of the the system reset signal to ensure complete initialization of the internal circuitry of the TNETX3110 before

there is any valid activity across the interface.

5. For receive data, TNETE2008 asserts the TH2COL signal during the appropriate slot time if it was asserted for any of the four bits

of data corresponding to that slot time.

6. For receive data, the TNETE2008 asserts the TH2RXDV signal only if there are four valid bits of data in the nibble.

TNETX3110 Datasheet(PDF) 52 Page - Texas Instruments

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