TNETX3270 datasheet(59/66 Pages) TI1

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TNETX3270

ThunderSWITCH

™ 24/3 ETHERNET™ SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DIO/DMA read cycle

timing requirements (see Figure 19)

NO.

MIN

MAX

UNIT

tw(SCSL)

Pulse duration, SCS low

tw(SCSH)

Pulse duration, SCS high

tsu(SRNW)

Setup time, SRNW high before SCS

↓

tsu(SAD)

Setup time, SAD1–SAD0 and SDMA valid before SCS

↓

operating characteristics over recommended operating conditions (see Figure 19)

NO.

PARAMETER

MIN

MAX

UNIT

tw(SRDYH)

Pulse duration, SRDY high

td(SRNW)

Delay time, from SRDY

↓ to SRNW↓

td(SAD)

Delay time, from SRDY

↓ to SAD1–SAD0 and SDMA invalid

td(SCS)

Delay time, from SRDY

↓ to SCS↑

td(SRDY)

Delay time, from SDATA7–SDATA0 to SRDY

↓

td(SRDYZH) Delay time, from SCS↓ to SRDY↑

td(SRDY)2

Delay time, from SCS

↓ to SRDY↓†

td(SDATAZ)

Delay time, from SCS

↑ to SDATA7–SDATA0 Z state

td(SRDY)3

Delay time, from SCS

↑ to SRDY↑

† When the switch is performing certain internal operations (e.g., EEPROM load), there may be a considerable delay (approximately 25–100 ms)

between SCS being asserted and SRDY being asserted.

SAD1–SAD0,

SDMA

(inputs)

SRNW

(input)

SCS

(input)

SDATA7–

SDATA0

(outputs)

SRDY

(output)

Figure 19. DIO/DMA Read Cycle

TNETX3270 Datasheet(PDF) 59 Page - Texas Instruments

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