ISL26321 datasheet(12/23 Pages) INTERSIL

12 / 23 page

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329

FN8273.0

June 8, 2012

Circuit Description

The ISL26320/21/22/23/24/25/29 family of 12-bit ADCs are

low-power Successive Approximation-type (SAR) ADCs with 1-,

2-, 4-, or 8-channels and a choice of single-ended or differential

inputs. The high-impedance buffered input simplifies interfacing

to sensors and external circuitry.

The entire ISL26320/21/22/23/24/25/29 family follows the

same base pinout and differs only in the analog input pins,

allowing the user to replicate the basic board layout across

multiple platforms with a minimum redesign effort.

The simple serial digital interface is compatible with popular

FPGAs and microcontrollers and allows direct conversion control

by the CNV pin.

Functional Description

The ISL26320/21/22/23/24/25/29 devices are SAR

(Successive Approximation Register) analog-to-digital converters

that use capacitor-based charge redistribution as their

conversion method.

These devices include an on-chip power-on reset (POR) circuit to

initialize the internal digital logic when power is applied. An

on-chip oscillator provides the master clock for the conversion

logic. The CNV signal controls when the converter enters into its

signal acquisition time (CNV = 0), and when it begins the

conversion sequence after the signal has been captured

(CNV = 1). The converters include a configuration register that

can be accessed via the serial port. The configuration register

has various bits to indicate which channel (where applicable) is

selected, to activate the auto-power-down feature where the ADC

is shut down between conversions, or to output the configuration

a conversion word is read from the serial port. The serial port

supports three different modes of reading the conversion data.

These will be discussed later in this data sheet.

Figures 19 and 20 illustrate simplified representations of the

converter analog section for differential and single-ended inputs,

respectively. During the acquisition phase (CNV = 0) the input

signal is presented to the Cs samples capacitors. To properly

sample the signal, the CNV signal must remain low for the

specified time. When CNV is taken high (CNV = 1), the switches

that connect the sampling capacitors to the input are opened

and the control logic begins the successive approximation

sequence to convert the captured signal into a digital word. The

conversion sequence timing is determined by the on-chip

oscillator.

ADC Transfer Function

The ISL26320, the ISL26322, and the ISL26324 feature

differential inputs with output data coding in two's complement

format (see Table 1). The size of one LSB in these devices is

(2*VREF)/4096. Figure 21 illustrates the ideal transfer function

for these devices.

The ISL26321, ISL26323, ISL26325, and ISL26329 feature

single-ended inputs with output coding in binary format (see

Table 2). The size of one LSB in these devices is VREF/4096.

Figure 22 illustrates the ideal transfer function for these devices.

FIGURE 19. ARCHITECTURAL BLOCK DIAGRAM, DIFFERENTIAL INPUT

FIGURE 20. ARCHITECTURAL BLOCK DIAGRAM, SINGLE-ENDED

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