4

6

8

10

12

14

16

0

20

40

60

80

100

120

140

160

180

200

Pstat + Pdyn + PCload2pF

Pstat + Pdyn + PCload8pF

f − Clock Frequency (MHz)

VDD=VDDO=2.625V

0

1

2

3

4

5

6

0

20

40

60

80

100

120

140

160

180

200

f − Clock Frequency (MHz)

VDDO=3.465V

VDDO=2.625V

VDDO=2.0V

VDDO=1.65V

CDCLVC1310

www.ti.com

SCAS917B

– JULY 2011 – REVISED FEBRUARY 2012

Figure 20. Device Power Consumption vs Clock

Figure 21. Device Power Consumption vs Clock

Frequency (VDD = VDDO = 3.465 V; Load 2 pF, 8

Frequency (VDD = VDDO = 2.625 V; Load 2 pF, 8

pF; per Output)

pF; per Output)

Figure 22. Dynamic Supply Current vs Clock Frequency (per Output)

Thermal Management

Power consumption of the CDCLVC1310 can be high enough to require attention to thermal management. For

reliability and performance reasons, the die temperature should be limited to a maximum of 125

°C. That is, as an

The device package has an exposed pad that provides the primary heat removal path as well as an electrical

grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal

landing pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of

the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.

A recommended land and via pattern is shown in Figure 23.

Copyright

© 2011–2012, Texas Instruments Incorporated

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