LDO

TPS7A4501

6V Input

5V

LDO

TPS79633

CDCE72010

DC/DC

TPS62291

3.3V

LDO

TPS79518

1.8V

6V

JP10

JP19

JP11

JP12

JP18

JP20

JP14

JP13

JP4

DC/DC

TPS62231

TRF3703

I/Q Mod

VCXO

AFE722x

AFE7225

TSW3100

Pattern Generator

Serialized LVDS

6x DAC Rate

Synchronous Clock

@ 1/8 DAC Rate

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Power Supply Options

5

Power Supply Options

The AFE722x EVM is designed to operate from an external 6 V wall wart supply. A LDO generates a 5V

rail for the TRF3703 IQ modulator as well as for the low noise LDOs which are generating a 3.3 V and 1.8

V rail for the AFE722x and the CDCE72010. Alternatively the 3.3 V and 1.8 V rails can be generated using

DC/DC converters which operate directly from the 6 V input for maximum power efficiency.

The EVM provides options to disable unused circuits by means of pin headers. These headers can also

be used for accurate power measurements where external power supplies can be directly connected to

them.

Three pin headers allow a convenient change between powering the AFE722x and CDCE72010 either

from DC/DC converter or low noise LDO.

6

Clocking Configuration

The AFE722x EVM offers 3 different options for

providing the clock to the AFE722x as well as the

supporting circuitry. The biggest challenge arises

when using the DAC with the TSW3100 because

the TSW3100 expects an input clock at 1/8 of the

DAC input data rate. However since the AFE722x

is designed for the serial LVDS interface, the DAC

data rate is 6x the actual AFE722x clock frequency.

Hence the clock to the TSW3100 needs to 6/8 =

3/4x the AFE722x clock frequency.

9

SLOU330

– December 2011

EVM Description

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© 2011, Texas Instruments Incorporated