TNETA1585 datasheet(27/32 Pages) TI1

Part #	TNETA1585

Description	ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES

PDF	32 Pages

Scroll/Zoom	100%

Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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27 / 32 page

TNETA1585

ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE

WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES

SDNS041A – NOVEMBER 1996 – REVISED JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Figure 10)

coprocessor interface (TCCX)

NO.

MIN

MAX

UNIT

tsu(TCCX)

Setup time, TCCX high before CLOCK

↑

th(TCCX)

Hold time, TCCX valid after CLOCK

↑

CLOCK

(input)

TCCX

(input)

Frame

Send

ACK

Scheduler

Source

Cell Type (3 bits)

CLP

DMA Number

(11 Bits)

Figure 10. TCCX Interface

timing requirements (see Figure 11)

coprocessor interface (RCCX)

NO.

MIN

MAX

UNIT

tsu(RCCX)

Setup time, RCCX high before CLOCK

↑

th(RCCX)

Hold time, RCCX valid after CLOCK

↑

RCCX

(input)

CLOCK

(input)

Frame

GCI

DMA Number (11 bits)

Figure 11. RCCX Interface

timing requirements (see Figure 12)

coprocessor interface (DAX)

NO.

MIN

MAX

UNIT

tsu(DAX)

Setup time, DAX high before CLOCK

↑

th(DAX)

Hold time, DAX valid after CLOCK

↑

DAX

(input)

CLOCK

(input)

Frame

DAV

DMA Number (11 bits)

Figure 12. DAX Interface

TNETA1585 Datasheet(PDF) 27 Page - Texas Instruments

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