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TNETE100PCE Datasheet(PDF) 19 Page - Texas Instruments |
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TNETE100PCE Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 26 page  ThunderLAN ™ TNETE100 PCI ETHERNET ™ CONTROLLER SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN ™ SPWS017B – APRIL 1995 – REVISED AUGUST 1996 19 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements for PCI 5-V and 3.3-V (continued) 5-V Clock 3.3-V Clock 0.8 V 2 V 1.5 V 0.475 × VDD 0.4 × VDD 0.325 × VDD Output Delay 3-State Output Input tc tw(H) tw(L) tVAL ton tsu th Inputs Valid Vmax toff Figure 4. PCI 5-V and 3.3-V Timing |
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