ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

21

POST OFFICE BOX 1443

MIN

MAX

UNIT

tsu

Setup time, data

250

ns

th

Hold time, data

0

ns

PARAMETER

MIN

MAX

UNIT

td(EADV-EXLEL)

Delay time, address high byte valid to EXLE low (address high byte setup time for external

latch)

0

ns

td(EXLEL-EADZ)

Delay time, EXLE low to address high byte invalid (address high byte hold time for external

latch)

10

ns

td(EADV-EALEL)

Delay time, address low byte valid to EALE low (address low byte setup time for external latch)

0

ns

td(EALEL-EADZ)

Delay time, EALE low to address low byte invalid (address low byte hold time for external latch)

10

ns

ta

Access time, address

288

ns

† The EPROM interface, consisting of 11 pins, requires only two TTL ’373 latches to latch the high and low addresses.

td(EADV-EXLEL)

EAD[7:0]

EXLE

EALE

EOE

td(EXLEL-EADZ)

ta

tsu

th

Data

td(EALEL-EADZ)

High

Address

Low

Address

td(EADV-EALEL)

Figure 8. BIOS ROM and LED Interface Timing