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TNETE110PCE Datasheet(PDF) 17 Page - Texas Instruments

Part # TNETE110PCE
Description  PCI ETHERNETE CONTROLLER SINGLE-CHIP 10 BASE-T
PDF  24 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TNETE110PCE Datasheet(HTML) 17 Page - Texas Instruments

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ThunderLAN
™ TNETE110
PCI ETHERNET
™ CONTROLLER
SINGLE-CHIP 10 BASE-T
SPWS018B – MARCH 1995 - REVISED MAY 1996
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
tVAL(PTP)
Delay time, PCLK to bused signals valid point-to-point (see Notes 15 and 16)
2
12
ns
ton
Float to active delay
2
ns
toff
Active to float delay
28
ns
NOTES: 14. Some of the timing symbols in this table currently are not listed with EIA or JEDEC standards for semiconductor symbology, but are
consistent with the PCI Local-Bus Specification, Revision 2.0.
15. Minimum times are measured with a 0-pF equivalent load; maximum times are measured with a 50-pF equivalent load. Actual test
capacitance can vary, but results should be correlated to these specifications.
16. PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT
has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.
timing requirements of PCI 5 V and 3.3 V (see Note 14 and Figure 4)
MIN
MAX
UNIT
tsu
Setup time, bused signals valid to PCLK (see Note 16)
7
ns
tsu(PTP)
Setup time to PCLK—point-to-point (see Note 16)
10, 12
ns
th
Hold time, input from PCLK
0
ns
tc
Cycle time, PCLK (see Note 17)
30
500
ns
tw(H)
Pulse duration, PCLK high
12
ns
tw(L)
Pulse duration, PCLK low
12
ns
tslew
Slew rate, PCLK (see Note 18)
1
4
V/ns
NOTES: 14. Some of the timing symbols in this table currently are not listed with EIA or JEDEC standards for semiconductor symbology, but are
consistent with the PCI Local-Bus Specification, Revision 2.0.
16. PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT
has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.
17. As a requirement for frame transmission /reception, the minimum PCLK frequency varies with network speed. The clock can only
be stopped in a low state.
18. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform.



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