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ADM3252EABCZ Datasheet(PDF) 12 Page - Analog Devices |
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ADM3252EABCZ Datasheet(HTML) 12 Page - Analog Devices |
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12 / 16 page ![]() ADM3252E Data Sheet Rev. 0 | Page 12 of 16 APPLICATIONS INFORMATION PCB LAYOUT The ADM3252E requires no external circuitry for its logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 20). Bypass capacitors are conveniently connected between Pin B1 and Pin C1 for VCC and between Pin C10 and Pin D10 for VISO. Figure 20. Recommended Printed Circuit Board Layout To suppress noise and reduce ripple, a parallel combination of at least two capacitors is recommended. The recommended capacitor values are 0.1 µF and 10 µF for both VCC and VISO. The smaller capacitor must have a low ESR; best practice suggests use of a ceramic capacitor. Do not exceed 2 mm for the total lead length between both ends of the low ESR capacitor and the input power supply pin. Because it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipating into the PCB through the ground pins. If the device is used at high ambient temperatures, take care to provide a thermal path from the ground pins to the PCB ground plane. The board layout in Figure 20 shows enlarged pads for the GND and GNDISO pins. The BGA balls are also grouped together to simplify layout and routing. To significantly reduce the temperature inside the chip, implement multiple vias from each of the pads to the ground plane. The dimensions of the expanded pads are at the discre- tion of the designer and the available board space. In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. The power supply section of the ADM3252E uses a 180 MHz oscillator frequency to pass power through its chip scale transformers. Operation at these high frequencies may raise concerns about radiated emissions and conducted noise. PCB layout and construction are very important tools for controlling radiated emissions. Refer to the AN-0971 Application Note, Recommendations for Control of Radiated Emissions with isoPower Devices, for extensive guidance on radiation mechanisms and board layout considerations. START-UP BEHAVIOR The ADM3252E does not contain a soft start circuit. Therefore, the start-up current and voltage behavior must be taken into account when designing with this device. When power is applied to VCC, the input switching circuit begins to operate and draw current when the UVLO minimum voltage is reached (approximately 2.7 V). The switching circuit drives the maximum available power to the output until it reaches the regulation voltage, which is where PWM control begins. The amount of current and the time required to reach regulation voltage depends on the load and the VCC slew rate. With a fast VCC slew rate (200 µs or less), the peak current draws up to 100 mA/V of VCC. The input voltage goes high faster than the output can turn on; therefore, the peak current is proportional to the maximum input voltage. With a slow VCC slew rate (in the millisecond range), the input voltage is not changing quickly when VCC reaches the UVLO minimum voltage. The current surge is approximately 300 mA because VCC is nearly constant at the 2.7 V UVLO voltage. The behavior during startup is similar to when the device load is a short circuit. When powering up the device, do not limit the current available to the VCC power pin to less than 300 mA. The ADM3252E device may not be able to drive the output to the regulation point if a current limiting device clamps the VCC voltage during startup. As a result, the ADM3252E device can draw large amounts of current at low voltage for extended periods of time. The output voltage of the ADM3252E device exhibits VISO overshoot to approximately 4 V during startup (see Figure 13 and Figure 14). If this overshoot could potentially damage compo- nents attached to VISO, a voltage limiting device, such as a Zener diode, can be used to clamp the voltage. A B C D E F G 9 10 8 11 7 5 6 4 2 3 1 H J K L C3 C1 C2 C4 A1 BALL CORNER VIA TO GNDISO VIA TO GNDISO 0.1µF 0.1µF |
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