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BL8521 Datasheet(PDF) 5 Page - SHANGHAI BELLING CO., LTD.

Part # BL8521
Description  3A Synchronous Buck Converter
PDF  8 Pages
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Manufacturer  BELLING [SHANGHAI BELLING CO., LTD.]
Direct Link  http://www.belling.com.cn
Logo BELLING - SHANGHAI BELLING CO., LTD.

BL8521 Datasheet(HTML) 5 Page - SHANGHAI BELLING CO., LTD.

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BL8521
5.5V, 1.4MHz, 3A Synchronous Buck Converter
requirements.
Dry
tantalum,
special
polymer,
aluminum electrolytic and ceramic capacitors are all
available
in
surface
mount
packages.
Special
polymer capacitors offer very low ESR but have
lower
capacitance
density
than
other
types.
Tantalum capacitors have the highest capacitance
density but it is important to only use types that have
been surge tested for use in switching power
supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-
sensitive applications provided that consideration is
given to ripple current ratings and long term
reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage
coefficient and audible piezoelectric effects. The
high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are
now becoming available in smaller case sizes. Their
high ripple current, high voltage rating and low ESR
make them ideal for switching regulator applications.
However, care must be taken when these capacitors
are used at the input and output. When a ceramic
capacitor is used at the input and the power is
supplied by a wall adapter through long wires, a load
step at the output can induce ringing at the input, VIN.
At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can
potentially cause a voltage spike at VIN large enough
to damage the part.
Checking Transient Response
The regulator loop response can be checked by
looking at the load transient response. Switching
regulators take several cycles to respond to a step
in load current. When a load step occurs, VOUT
immediately shifts by an amount equal to
ILOAD(ESR),
where ESR is the effective series resistance of COUT.
ILOAD also begins to charge or discharge COUT
generating a feedback error signal used by the
regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem. The COMP pin external components and
output capacitor shown in Typical Application Circuit
will
provide
adequate
compensation
for
most
applications.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%.
It is often useful to analyze individual losses to
determine what is limiting the efficiency and which
change would produce the most improvement.
Efficiency can be expressed as :
Efficiency = 100%
(L1+ L2+ L3+ ...) where L1, L2,
etc. are the individual losses as a percentage of
input power. Although all dissipative elements in the
circuit produce losses, two main sources usually
account for most of the losses: VDD quiescent
current and I
2R losses.
The VDD quiescent current loss dominates the
efficiency loss at very low load currents whereas the
I
2R loss dominates the efficiency loss at medium to
high load current. In a typical efficiency plot, the
efficiency curve at very low load currents can be
misleading since the actual power lost is of no
consequence.
1. The VDD quiescent current is due to two
components: the DC bias current as given in the
electrical characteristics and the internal main switch
and synchronous switch gate charge currents. The
gate charge current results from switching the gate
capacitance of the internal power MOSFET switches.
Each time the gate is switched from high to low to
high again, a packet of charge
Q moves from VDD
to ground. The resulting
Q/t is the current out of
VDD that is typically larger than the DC bias current.
In continuous mode, IGATECHG = f(QT+QB) where QT
and QB are the gate charges of the internal top and
bottom switches.
Both the DC bias and gate charge losses are
proportional to VDD and thus their effects will be
more pronounced at higher supply voltages.
2. I
2R losses are calculated from the resistances of
the internal switches, RSW and external inductor RL.
In continuous mode the average output current
flowing through inductor L is “chopped” between the
main switch and the synchronous switch. Thus, the
series resistance looking into the LX pin is a function
of both top and bottom MOSFET RDS(ON) and the
duty cycle (D) as follows :
RSW = RDS(ON)TOP x D + RDS(ON)BOT x (1"D)
The RDS(ON) for both the top and bottom MOSFETs
can be obtained from the Typical Performance
Characteristics curves. Thus, to obtain I
2R losses,
simply add RSW to RL and multiply the result by the
square of the average output current. Other losses
including CIN and COUT ESR dissipative losses and



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