AD9645 datasheet(6/36 Pages) AD

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AD9645

Data Sheet

Rev. 0 | Page 6 of 36

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter1, 2

Temp

Min

Typ

Max

Unit

CLOCK3

Input Clock Rate

Full

1000

MHz

Conversion Rate

Full

80/125

MSPS

Clock Pulse Width High (t

EH)

Full

6.25/4.00

Clock Pulse Width Low (t

EL)

Full

6.25/4.00

OUTPUT PARAMETERS3

Propagation Delay (t

PD)

Full

2.3

Rise Time (t

R) (20% to 80%)

Full

300

Fall Time (t

F) (20% to 80%)

Full

300

FCO Propagation Delay (t

FCO)

Full

1.5

2.3

3.1

DCO Propagation Delay (t

CPD)

Full

FCO + (tSAMPLE/16)

DCO to Data Delay (t

DATA)

Full

SAMPLE/16) − 300

SAMPLE/16

SAMPLE/16) + 300

DCO to FCO Delay (t

FRAME)

Full

SAMPLE/16) − 300

SAMPLE/16

SAMPLE/16) + 300

Lane Delay (t

LD)

Data-to-Data Skew (t

DATA-MAX − tDATA-MIN)

Full

±50

±200

Wake-Up Time (Standby)

25°C

250

Wake-Up Time (Power-Down)5

25°C

375

μs

Pipeline Latency

Full

Clock

cycles

APERTURE

Aperture Delay (t

25°C

Aperture Uncertainty (Jitter, t

25°C

174

fs rms

Out-of-Range Recovery Time

25°C

Clock

cycles

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2 Measured on standard FR-4 material.

3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.

4 t

SAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS.

5 Wake-up time is defined as the time required to return to normal operation from power-down mode.

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Limit

Unit

SPI TIMING REQUIREMENTS

See Figure 68

Setup time between the data and the rising edge of SCLK

ns min

Hold time between the data and the rising edge of SCLK

ns min

CLK

Period of the SCLK

ns min

Setup time between CSB and SCLK

ns min

Hold time between CSB and SCLK

ns min

HIGH

SCLK pulse width high

ns min

LOW

SCLK pulse width low

ns min

EN_SDIO

Time required for the SDIO pin to switch from an input to an output relative

to the SCLK falling edge (not shown in Figure 68)

ns min

DIS_SDIO

Time required for the SDIO pin to switch from an output to an input relative

to the SCLK rising edge (not shown in Figure 68)

ns min

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