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CXD2597Q Datasheet(PDF) 5 Page - Sony Corporation |
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CXD2597Q Datasheet(HTML) 5 Page - Sony Corporation |
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5 / 115 page  – 5 – CXD2597Q Pin No. Symbol I/O Description Test pin. Normally, GND. Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. RF signal input. Analog GND. Operational amplifier constant current input. Analog power supply. EFM full-swing output. (low = Vss, high = VDD) Asymmetry comparator voltage input. Asymmetry circuit constant current input. EFM signal input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter output. (slave = digital PLL) Master PLL filter input. Master PLL charge pump output. Analog power supply. Wide-band EFM PLL VCO2 control voltage input. Wide-band EFM PLL charge pump output. Digital GND. Digital power supply. Digital Out output. D/A interface. LR clock output f = Fs. D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Bit clock output. Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. Master clock power supply. Crystal oscillation circuit input. Master clock is externally input from this pin. Crystal oscillation circuit output. Master clock GND. Analog power supply. L ch analog output. L ch operational amplifier input. — — 1, 0 — Analog 1, Z, 0 — 1, Z, 0 — — 1, 0 1, 0 1, 0 1, 0 1, 0 — — — I I I I I I I — I — O I I I — I O I O — I O — — O O O O O — I O — — O I TES1 XTSL VC FE SE TE RFDC AVSS0 IGEN AVDD0 ASYO ASYI BIAS RFAC AVSS3 CLTV FILO FILI PCO AVDD3 VCTL VPCO VSS VDD DOUT LRCK PCMD BCK EMPH XVDD XTAI XTAO XVSS AVDD1 AOUT1 AIN1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 |
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