TSC102 datasheet(7/24 Pages) STMICROELECTRONICS

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TSC102

Electrical characteristics

Doc ID 16754 Rev 2

7/24

Table 9.

Signal conditioning amplifier

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Vicm

Common mode voltage range

Tmin < Tamb < Tmax

0Vcc

VIO

Input offset voltage

Va2 =1V

Tamb =25° C

-40° C < Tamb < 150° C

±3.5

±4.5

ΔVIO

Input offset voltage drift

Tmin < Tamb < Tmax

5µV/°C

Iib

Input bias current

Va2 =Va3 =VCC/2

Voh2

Output high-level saturation

voltage (Voh2 =VCC-Vout)

Va2 =1V Va3 =0V Iout =1mA

-40° C< Tamb < 125° C

185

Vol2

Output low-level saturation voltage

Va2 =0V Va3 =1V

Iout =1mA

-40° C< Tamb < 125° C

165

Isc2

Short-circuit current

Out connected to VCC or Gnd

ΔVout/ΔIout Output stage load regulation

-10 mA < Iout < +10 mA

Va2 =1V

Iout sink or source current

300

µV/mA

CMR2

DC common mode rejection

Variation of VIO versus Vicm

Tmin < Tamb < Tmax

0V<Va2<3 V

0V<Va2<5 V

SVR2

Supply voltage rejection

Variation of VIO versus VCC

3.5 V<VCC<5.5 V

Va2 =1V

-40° C < Tamb < 125° C

105

GBP

Gain bandwidth product

RL =10kΩ, Cload =100 pF,

f=100kHz

1MHz

Phase margin

RL =10kΩ, Cload = 100 pF

deg

Slew rate

RL =10kΩ, Cload =100 pF

Va2 = 0.5 V to 4.5 V

A3 connected to OUT (follower

configuration)

Slew rate measured from 10%

to 90% of Vout step

0.2

0.4

V/µs

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