PXS20 datasheet(79/119 Pages) FREESCALE

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Electrical characteristics

PXS20 Microcontroller Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

3.7

Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance:

•

A supply overvoltage is applied to each power supply pin.

•

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

3.8

Voltage regulator electrical characteristics

The voltage regulator is composed of the following blocks:

•

High power regulator HPREG1 (internal ballast to support core current)

•

High power regulator HPREG2 (external NPN to support core current)

•

Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO)

•

Low voltage detector (LVD_MAIN_2) for 3.3 V supply (VDDREG)

•

Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH)

•

Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPVDD)

•

Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN

•

High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPVDD)

•

High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.

•Power on Reset (POR)

HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on

board to supply core current. The PXS20 always powers up using HPREG1 if an external NPN transistor is present. Then the

PXS20 makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational, the

controller part of HPREG1 is switched off. The following bipolar transistors are supported:

•

BCP68 from ON Semiconductor

Table 14. ESD ratings1, 2

1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated

Circuits.

2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

No.

Symbol

Parameter

Conditions

Class

Max value3

3 Data based on characterization results, not tested in production.

Unit

1VESD(HBM)

SR Electrostatic discharge

(Human Body Model)

TA =25 °C

conforming to AEC-Q100-002

H1C

2000

2VESD(MM)

SR Electrostatic discharge

(Machine Model)

TA =25 °C

conforming to AEC-Q100-003

200

3VESD(CDM)

SR Electrostatic discharge

(Charged Device Model)

TA =25 °C

conforming to AEC-Q100-011

C3A

500

750 (corners)

Table 15. Latch-up results

No.

Symbol

Parameter

Conditions

Class

Static latch-up class

TA = 125 °C conforming to JESD 78

II level A

PXS20 Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

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