RT8855 datasheet(13/18 Pages) RICHTEK

13 / 18 page

RT8855

DS8855-01 April 2011

www.richtek.com

CORE Section- Differential Output Voltage Sensing

The RT8855 uses differential voltage sensing by a high

gain low offset ErrorAmp as shown in Figure 7. Connect

the negative on-die CPU remote sense pin to FBRTN.

Connect the positive on-die remote sense pin to FB with

a resistor (RFB) The ErrorAmp compares EAP

( = VDAC

− VADJ) with the VFB to regulate the output voltage.

CORE Section- Programmable Load-line

Output current of CSA is summed and averaged in

RT8855. Then 0.5

Σ (IX[n]) is sent to ADJ pin. Because

Σ IX[n] is a PTC (Positive Temperature Coefficient) current,

an NTC (Negative Temperature Coefficient) resistor is

needed to connect ADJ pin to GND. If the NTC resistor is

properly selected to compensate the temperature

coefficient of IX[n], the voltage on ADJ pin will be

proportional to IOUT without temperature effect. In RT8855,

the positive input of ErrorAmp is

“V

DAC

− VADJ”. VOUT will

“V

DAC

− VADJ”, too. Thus, the output voltage

decreasing linearly with IOUT is obtained. The loadline is

defined as :

OUT

ADJ

OUT

CSN

LL(loadline)

DCR

ΔΔ

= ×

ΔΔ

Briefly, the resistance of RADJ sets the resistance of

loadline. The temperature coefficient of RADJ compensates

the temperature effect of loadline.

CORE Section- Load Transient Quick Response

In steady state, the voltage of VFB is controlled to be very

close to VEAP. While a load step transient from light load

to heavy load could cause VFB lower than VEAP by several

tens of mV. In prior design, owing to limited control

bandwidth, controller is hard to prevent VOUT undershoot

during quick load transient from light load to heavy load.

RT8855 buit in proprietary Burst Transient Response

(BTRTM ) technology, that detects load transient by

comparing VFB and VEAP. If VFB suddenly drops below

“V

EAP

− VOR”, VQR is a predetermined voltage. The quick

response indicator QR rises up. When QR = high, RT8855

turns on all high side MOSFETs and turn off all low side

MOSFETs. The sensitivity of quick response can be

adjusted by the values of CFB and RFB. Smaller RFB and/

or larger CFB will make QR easier to be trigger. Figure8 is

the circuit and typical waveforms.

CORE Section- No-Load Offset

In Figure 7, IOFSP and IOFSN are used to generate no-load

offset. Either IOFSP or IOFSN is active during normal operation.

Connect a resistor from OFS pin to GND to activate IOFSN.

IOFSN flows through RFB from FB pin to VCCP. In this case,

negative no-load offset voltage (VOFSN) is generated.

Connect a resistor from OFS pin to 5VCC to activate IOFSP.

IOFSP flows through RFB from the VCCP to FB pin. In this

case, positive no-load offset voltage (VOFSP) is generated.

Beside IOFSN and IOFSP, the RT8855 generates another DC

current for initial no-load negative offset. A DC current

source will continuously inject typical 9uA current into

the resistors connected to ADJ pin, Therefore, the effect

of this 9uA current source and ADJ resistors should

counted into the calculation of no-load offset :

OFSN

ADJ

OFS

9u R

0.4

9u R

=×

OFSP

ADJ

OFS

9u R

0.4

9u R

=×

−

=×

−

Figure 7. Circuit for VCORE Differential Sensing and No

load Offest.

CFB

RFB

VCCP

(Positive remote

sense pin of CPU)

VDAC

EAP

COMP

FBRTN

ADJ

VCCN

(Negative remote

sense pin of CPU)

RADJ

IOFSN

IOFSP

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